hwmon: (coretemp) Fix checkpatch errors
Fix remaining checkpatch errors in the coretemp driver. Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Durgadoss R <durgadoss.r@intel.com> Acked-by: Jean Delvare <khali@linux-fr.org>
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5e99c2f1e0
Коммит
4cc452758f
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@ -35,9 +35,9 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/cpu.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <asm/msr.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/smp.h>
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#define DRVNAME "coretemp"
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#define DRVNAME "coretemp"
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@ -170,7 +170,7 @@ static ssize_t show_temp(struct device *dev,
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/* Check whether the data is valid */
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/* Check whether the data is valid */
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if (eax & 0x80000000) {
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if (eax & 0x80000000) {
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tdata->temp = tdata->tjmax -
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tdata->temp = tdata->tjmax -
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(((eax >> 16) & 0x7f) * 1000);
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((eax >> 16) & 0x7f) * 1000;
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tdata->valid = 1;
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tdata->valid = 1;
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}
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}
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tdata->last_updated = jiffies;
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tdata->last_updated = jiffies;
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@ -193,9 +193,8 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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/* Early chips have no MSR for TjMax */
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/* Early chips have no MSR for TjMax */
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if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
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if (c->x86_model == 0xf && c->x86_mask < 4)
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usemsr_ee = 0;
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usemsr_ee = 0;
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}
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/* Atom CPUs */
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/* Atom CPUs */
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@ -214,14 +213,14 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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pci_dev_put(host_bridge);
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pci_dev_put(host_bridge);
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}
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}
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if ((c->x86_model > 0xe) && (usemsr_ee)) {
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if (c->x86_model > 0xe && usemsr_ee) {
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u8 platform_id;
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u8 platform_id;
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/* Now we can detect the mobile CPU using Intel provided table
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/*
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http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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* Now we can detect the mobile CPU using Intel provided table
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For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
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* http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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*/
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* For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
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*/
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err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
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err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
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if (err) {
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if (err) {
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dev_warn(dev,
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dev_warn(dev,
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@ -229,20 +228,26 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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" CPU\n");
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" CPU\n");
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usemsr_ee = 0;
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usemsr_ee = 0;
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} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
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} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
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/* Trust bit 28 up to Penryn, I could not find any
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/*
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documentation on that; if you happen to know
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* Trust bit 28 up to Penryn, I could not find any
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someone at Intel please ask */
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* documentation on that; if you happen to know
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* someone at Intel please ask
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*/
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usemsr_ee = 0;
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usemsr_ee = 0;
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} else {
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} else {
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/* Platform ID bits 52:50 (EDX starts at bit 32) */
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/* Platform ID bits 52:50 (EDX starts at bit 32) */
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platform_id = (edx >> 18) & 0x7;
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platform_id = (edx >> 18) & 0x7;
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/* Mobile Penryn CPU seems to be platform ID 7 or 5
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/*
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(guesswork) */
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* Mobile Penryn CPU seems to be platform ID 7 or 5
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if ((c->x86_model == 0x17) &&
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* (guesswork)
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((platform_id == 5) || (platform_id == 7))) {
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*/
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/* If MSR EE bit is set, set it to 90 degrees C,
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if (c->x86_model == 0x17 &&
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otherwise 105 degrees C */
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(platform_id == 5 || platform_id == 7)) {
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/*
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* If MSR EE bit is set, set it to 90 degrees C,
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* otherwise 105 degrees C
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*/
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tjmax_ee = 90000;
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tjmax_ee = 90000;
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tjmax = 105000;
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tjmax = 105000;
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}
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}
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@ -250,7 +255,6 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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}
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}
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if (usemsr_ee) {
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if (usemsr_ee) {
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err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
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err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
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if (err) {
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if (err) {
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dev_warn(dev,
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dev_warn(dev,
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@ -259,9 +263,11 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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} else if (eax & 0x40000000) {
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} else if (eax & 0x40000000) {
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tjmax = tjmax_ee;
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tjmax = tjmax_ee;
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}
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}
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/* if we dont use msr EE it means we are desktop CPU (with exeception
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of Atom) */
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} else if (tjmax == 100000) {
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} else if (tjmax == 100000) {
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/*
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* If we don't use msr EE it means we are desktop CPU
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* (with exeception of Atom)
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*/
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dev_warn(dev, "Using relative temperature scale!\n");
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dev_warn(dev, "Using relative temperature scale!\n");
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}
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}
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@ -275,8 +281,10 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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u32 eax, edx;
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u32 eax, edx;
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u32 val;
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u32 val;
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/* A new feature of current Intel(R) processors, the
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/*
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IA32_TEMPERATURE_TARGET contains the TjMax value */
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* A new feature of current Intel(R) processors, the
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* IA32_TEMPERATURE_TARGET contains the TjMax value
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*/
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err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (err) {
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if (err) {
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dev_warn(dev, "Unable to read TjMax from CPU.\n");
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dev_warn(dev, "Unable to read TjMax from CPU.\n");
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@ -286,7 +294,7 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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* If the TjMax is not plausible, an assumption
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* If the TjMax is not plausible, an assumption
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* will be used
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* will be used
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*/
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*/
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if ((val > 80) && (val < 120)) {
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if (val > 80 && val < 120) {
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dev_info(dev, "TjMax is %d C.\n", val);
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dev_info(dev, "TjMax is %d C.\n", val);
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return val * 1000;
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return val * 1000;
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}
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}
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@ -331,7 +339,7 @@ static int get_pkg_tjmax(unsigned int cpu, struct device *dev)
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (!err) {
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if (!err) {
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val = (eax >> 16) & 0xff;
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val = (eax >> 16) & 0xff;
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if ((val > 80) && (val < 120))
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if (val > 80 && val < 120)
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return val * 1000;
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return val * 1000;
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}
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}
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dev_warn(dev, "Unable to read Pkg-TjMax from CPU:%u\n", cpu);
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dev_warn(dev, "Unable to read Pkg-TjMax from CPU:%u\n", cpu);
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@ -399,7 +407,7 @@ static void update_ttarget(__u8 cpu_model, struct temp_data *tdata,
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* on older CPUs but not in this register,
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* on older CPUs but not in this register,
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* Atoms don't have it either.
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* Atoms don't have it either.
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*/
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*/
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if ((cpu_model > 0xe) && (cpu_model != 0x1c)) {
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if (cpu_model > 0xe && cpu_model != 0x1c) {
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err = rdmsr_safe_on_cpu(tdata->cpu,
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err = rdmsr_safe_on_cpu(tdata->cpu,
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MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (err) {
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if (err) {
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@ -407,7 +415,7 @@ static void update_ttarget(__u8 cpu_model, struct temp_data *tdata,
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"Unable to read IA32_TEMPERATURE_TARGET MSR\n");
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"Unable to read IA32_TEMPERATURE_TARGET MSR\n");
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} else {
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} else {
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tdata->ttarget = tdata->tjmax -
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tdata->ttarget = tdata->tjmax -
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(((eax >> 8) & 0xff) * 1000);
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((eax >> 8) & 0xff) * 1000;
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}
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}
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}
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}
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}
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}
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@ -423,7 +431,7 @@ static int chk_ucode_version(struct platform_device *pdev)
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* Readings might stop update when processor visited too deep sleep,
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* Readings might stop update when processor visited too deep sleep,
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* fixed for stepping D0 (6EC).
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* fixed for stepping D0 (6EC).
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*/
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*/
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if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
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if (c->x86_model == 0xe && c->x86_mask < 0xc) {
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/* check for microcode update */
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/* check for microcode update */
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err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu,
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err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu,
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&edx, 1);
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&edx, 1);
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@ -791,7 +799,6 @@ static struct notifier_block coretemp_cpu_notifier __refdata = {
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.notifier_call = coretemp_cpu_callback,
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.notifier_call = coretemp_cpu_callback,
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};
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};
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static int __init coretemp_init(void)
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static int __init coretemp_init(void)
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{
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{
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int i, err = -ENODEV;
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int i, err = -ENODEV;
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