dt-bindings: timer: Convert ARM timer bindings to json-schema
Convert ARM timers to DT schema format using json-schema. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
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* ARM architected timer
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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** CP15 Timer node properties:
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- compatible : Should at least contain one of
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"arm,armv7-timer"
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"arm,armv8-timer"
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- interrupts : Interrupt list for secure, non-secure, virtual and
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hypervisor timers, in that order.
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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- fsl,erratum-a008585 : A boolean property. Indicates the presence of
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QorIQ erratum A-008585, which says that reading the counter is
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unreliable unless the same value is returned by back-to-back reads.
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This also affects writes to the tval register, due to the implicit
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counter read.
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- hisilicon,erratum-161010101 : A boolean property. Indicates the
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presence of Hisilicon erratum 161010101, which says that reading the
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counters is unreliable in some cases, and reads may return a value 32
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beyond the correct value. This also affects writes to the tval
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registers, due to the implicit counter read.
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** Optional properties:
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- arm,cpu-registers-not-fw-configured : Firmware does not initialize
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any of the generic timer CPU registers, which contain their
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architecturally-defined reset values. Only supported for 32-bit
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systems which follow the ARMv7 architected reset values.
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- arm,no-tick-in-suspend : The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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Example:
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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** Memory mapped timer node properties:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only when firmware has not configured the MMIO CNTFRQ registers.
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- reg : The control frame base address.
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Note that #address-cells, #size-cells, and ranges shall be present to ensure
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the CPU can address a frame's registers.
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A timer node has up to 8 frame sub-nodes, each with the following properties:
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- frame-number: 0 to 7.
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- interrupts : Interrupt list for physical and virtual timers in that order.
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The virtual timer interrupt is optional.
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- reg : The first and second view base addresses in that order. The second view
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base address is optional.
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- status : "disabled" indicates the frame is not available for use. Optional.
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Example:
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame@f0001000 {
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frame-number = <0>
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame@f0003000 {
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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};
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};
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@ -0,0 +1,103 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM architected timer
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maintainers:
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- Marc Zyngier <marc.zyngier@arm.com>
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- Mark Rutland <mark.rutland@arm.com>
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description: |+
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- arm,cortex-a15-timer
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- enum:
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- arm,armv7-timer
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- items:
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- enum:
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- arm,armv7-timer
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- items:
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- enum:
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- arm,armv8-timer
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interrupts:
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items:
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- description: secure timer irq
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- description: non-secure timer irq
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- description: virtual timer irq
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- description: hypervisor timer irq
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clock-frequency:
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description: The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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always-on:
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type: boolean
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description: If present, the timer is powered through an always-on power
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domain, therefore it never loses context.
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fsl,erratum-a008585:
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type: boolean
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description: Indicates the presence of QorIQ erratum A-008585, which says
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that reading the counter is unreliable unless the same value is returned
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by back-to-back reads. This also affects writes to the tval register, due
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to the implicit counter read.
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hisilicon,erratum-161010101:
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type: boolean
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description: Indicates the presence of Hisilicon erratum 161010101, which
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says that reading the counters is unreliable in some cases, and reads may
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return a value 32 beyond the correct value. This also affects writes to
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the tval registers, due to the implicit counter read.
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arm,cpu-registers-not-fw-configured:
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type: boolean
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description: Firmware does not initialize any of the generic timer CPU
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registers, which contain their architecturally-defined reset values. Only
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supported for 32-bit systems which follow the ARMv7 architected reset
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values.
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arm,no-tick-in-suspend:
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type: boolean
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description: The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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required:
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- compatible
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oneOf:
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- required:
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- interrupts
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- required:
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- interrupts-extended
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examples:
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- |
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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...
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@ -0,0 +1,120 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM memory mapped architected timer
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maintainers:
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- Marc Zyngier <marc.zyngier@arm.com>
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- Mark Rutland <mark.rutland@arm.com>
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description: |+
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ARM cores may have a memory mapped architected timer, which provides up to 8
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frames with a physical and optional virtual timer per frame.
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The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
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properties:
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compatible:
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items:
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- enum:
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- arm,armv7-timer-mem
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reg:
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maxItems: 1
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description: The control frame base address
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'#address-cells':
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enum: [1, 2]
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'#size-cells':
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const: 1
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clock-frequency:
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description: The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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always-on:
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type: boolean
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description: If present, the timer is powered through an always-on power
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domain, therefore it never loses context.
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arm,cpu-registers-not-fw-configured:
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type: boolean
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description: Firmware does not initialize any of the generic timer CPU
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registers, which contain their architecturally-defined reset values. Only
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supported for 32-bit systems which follow the ARMv7 architected reset
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values.
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arm,no-tick-in-suspend:
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type: boolean
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description: The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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patternProperties:
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'^frame@[0-9a-z]*$':
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description: A timer node has up to 8 frame sub-nodes, each with the following properties.
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properties:
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frame-number:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- minimum: 0
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maximum: 7
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interrupts:
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minItems: 1
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maxItems: 2
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items:
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- description: physical timer irq
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- description: virtual timer irq
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reg :
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minItems: 1
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maxItems: 2
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items:
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- description: 1st view base address
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- description: 2nd optional view base address
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required:
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- frame-number
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- interrupts
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- reg
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required:
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- compatible
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- reg
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- '#address-cells'
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- '#size-cells'
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examples:
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- |
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame@f0001000 {
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frame-number = <0>;
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame@f0003000 {
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frame-number = <1>;
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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};
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};
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...
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@ -1,27 +0,0 @@
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* ARM Global Timer
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Cortex-A9 are often associated with a per-core Global timer.
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** Timer node required properties:
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- compatible : should contain
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* "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
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* "arm,cortex-a9-global-timer" for Cortex-A9 global
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timers or any compatible implementation. Note: driver
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supports versions r2p0 and above.
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- interrupts : One interrupt to each core
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- reg : Specify the base address and the size of the GT timer
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register window.
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- clocks : Should be phandle to a clock.
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Example:
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timer@2c000600 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x2c000600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&arm_periph_clk>;
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};
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@ -0,0 +1,46 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/arm,global_timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Global Timer
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maintainers:
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- Stuart Menefy <stuart.menefy@st.com>
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description:
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Cortex-A9 are often associated with a per-core Global timer.
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properties:
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compatible:
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items:
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- enum:
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- arm,cortex-a5-global-timer
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- arm,cortex-a9-global-timer
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description: driver supports versions r2p0 and above.
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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examples:
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- |
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timer@2c000600 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x2c000600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&arm_periph_clk>;
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};
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...
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