ARM: plat-mxc: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
This commit is contained in:
Родитель
b9858efad3
Коммит
4d93579f63
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@ -60,7 +60,6 @@
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#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
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static void __iomem *brd_io;
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static void expio_ack_irq(u32 irq);
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static struct resource smsc911x_resources[] = {
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{
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@ -93,7 +92,8 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
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u32 int_valid;
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u32 expio_irq;
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desc->chip->mask(irq); /* irq = gpio irq number */
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/* irq = gpio irq number */
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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imr_val = __raw_readw(brd_io + INTR_MASK_REG);
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int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
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@ -110,37 +110,37 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
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d->handle_irq(expio_irq, d);
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}
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desc->chip->ack(irq);
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desc->chip->unmask(irq);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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}
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/*
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* Disable an expio pin's interrupt by setting the bit in the imr.
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* Irq is an expio virtual irq number
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*/
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static void expio_mask_irq(u32 irq)
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static void expio_mask_irq(struct irq_data *d)
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{
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u16 reg;
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
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reg = __raw_readw(brd_io + INTR_MASK_REG);
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reg |= (1 << expio);
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__raw_writew(reg, brd_io + INTR_MASK_REG);
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}
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static void expio_ack_irq(u32 irq)
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static void expio_ack_irq(struct irq_data *d)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
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__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
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__raw_writew(0, brd_io + INTR_RESET_REG);
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expio_mask_irq(irq);
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expio_mask_irq(d);
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}
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static void expio_unmask_irq(u32 irq)
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static void expio_unmask_irq(struct irq_data *d)
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{
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u16 reg;
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
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reg = __raw_readw(brd_io + INTR_MASK_REG);
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reg &= ~(1 << expio);
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@ -148,9 +148,9 @@ static void expio_unmask_irq(u32 irq)
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}
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static struct irq_chip expio_irq_chip = {
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.ack = expio_ack_irq,
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.mask = expio_mask_irq,
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.unmask = expio_unmask_irq,
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.irq_ack = expio_ack_irq,
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.irq_mask = expio_mask_irq,
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.irq_unmask = expio_unmask_irq,
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};
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int __init mxc_expio_init(u32 base, u32 p_irq)
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@ -89,22 +89,22 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
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#endif /* CONFIG_FIQ */
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/* Disable interrupt number "irq" in the AVIC */
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static void mxc_mask_irq(unsigned int irq)
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static void mxc_mask_irq(struct irq_data *d)
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{
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__raw_writel(irq, avic_base + AVIC_INTDISNUM);
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__raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
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}
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/* Enable interrupt number "irq" in the AVIC */
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static void mxc_unmask_irq(unsigned int irq)
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static void mxc_unmask_irq(struct irq_data *d)
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{
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__raw_writel(irq, avic_base + AVIC_INTENNUM);
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__raw_writel(d->irq, avic_base + AVIC_INTENNUM);
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}
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static struct mxc_irq_chip mxc_avic_chip = {
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.base = {
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.ack = mxc_mask_irq,
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.mask = mxc_mask_irq,
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.unmask = mxc_unmask_irq,
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.irq_ack = mxc_mask_irq,
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.irq_mask = mxc_mask_irq,
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.irq_unmask = mxc_unmask_irq,
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},
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#ifdef CONFIG_MXC_IRQ_PRIOR
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.set_priority = avic_irq_set_priority,
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@ -63,29 +63,29 @@ static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
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__raw_writel(l, port->base + GPIO_IMR);
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}
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static void gpio_ack_irq(u32 irq)
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static void gpio_ack_irq(struct irq_data *d)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio = irq_to_gpio(d->irq);
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_clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
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}
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static void gpio_mask_irq(u32 irq)
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static void gpio_mask_irq(struct irq_data *d)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio = irq_to_gpio(d->irq);
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_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
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}
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static void gpio_unmask_irq(u32 irq)
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static void gpio_unmask_irq(struct irq_data *d)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio = irq_to_gpio(d->irq);
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_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
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}
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static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
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static int gpio_set_irq_type(u32 irq, u32 type)
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static int gpio_set_irq_type(struct irq_data *d, u32 type)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio = irq_to_gpio(d->irq);
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struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
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u32 bit, val;
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int edge;
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@ -211,9 +211,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int gpio_set_wake_irq(u32 irq, u32 enable)
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static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio = irq_to_gpio(d->irq);
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u32 gpio_idx = gpio & 0x1F;
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struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
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@ -233,11 +233,11 @@ static int gpio_set_wake_irq(u32 irq, u32 enable)
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}
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static struct irq_chip gpio_irq_chip = {
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.ack = gpio_ack_irq,
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.mask = gpio_mask_irq,
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.unmask = gpio_unmask_irq,
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.set_type = gpio_set_irq_type,
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.set_wake = gpio_set_wake_irq,
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.irq_ack = gpio_ack_irq,
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.irq_mask = gpio_mask_irq,
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.irq_unmask = gpio_unmask_irq,
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.irq_set_type = gpio_set_irq_type,
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.irq_set_wake = gpio_set_wake_irq,
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};
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static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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@ -69,50 +69,50 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
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#endif
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/**
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* tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
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* tzic_mask_irq() - Disable interrupt source "d" in the TZIC
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*
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* @param irq interrupt source number
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* @param d interrupt source
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*/
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static void tzic_mask_irq(unsigned int irq)
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static void tzic_mask_irq(struct irq_data *d)
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{
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int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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index = d->irq >> 5;
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off = d->irq & 0x1F;
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__raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
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}
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/**
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* tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
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* tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
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*
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* @param irq interrupt source number
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* @param d interrupt source
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*/
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static void tzic_unmask_irq(unsigned int irq)
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static void tzic_unmask_irq(struct irq_data *d)
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{
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int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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index = d->irq >> 5;
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off = d->irq & 0x1F;
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__raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
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}
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static unsigned int wakeup_intr[4];
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/**
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* tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
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* tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
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*
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* @param irq interrupt source number
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* @param d interrupt source
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* @param enable enable as wake-up if equal to non-zero
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* disble as wake-up if equal to zero
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*
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* @return This function returns 0 on success.
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*/
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static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
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static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
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{
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unsigned int index, off;
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index = irq >> 5;
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off = irq & 0x1F;
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index = d->irq >> 5;
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off = d->irq & 0x1F;
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if (index > 3)
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return -EINVAL;
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@ -128,10 +128,10 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
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static struct mxc_irq_chip mxc_tzic_chip = {
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.base = {
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.name = "MXC_TZIC",
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.ack = tzic_mask_irq,
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.mask = tzic_mask_irq,
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.unmask = tzic_unmask_irq,
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.set_wake = tzic_set_wake_irq,
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.irq_ack = tzic_mask_irq,
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.irq_mask = tzic_mask_irq,
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.irq_unmask = tzic_unmask_irq,
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.irq_set_wake = tzic_set_wake_irq,
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},
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#ifdef CONFIG_FIQ
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.set_irq_fiq = tzic_set_irq_fiq,
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