Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
Pull ARM cpufreq drivers updates for v5.7 from Viresh Kumar: "This pull request contains: - update to imx cpufreq drivers to improve their support (Anson Huang, Christoph Niedermaier, and Peng Fan). - Update to qcom cpufreq to support other krait based SoCs (Ansuel Smith). - Update ti cpufreq driver to support OPP_PLUS (Lokesh Vutla). - Update cpufreq-dt driver to allow platfoem specific intermediate callbacks (Peng Fan)." * 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: qcom: Add support for krait based socs cpufreq: imx6q-cpufreq: Improve the logic of -EPROBE_DEFER handling cpufreq: dt: Allow platform specific intermediate callbacks cpufreq: imx-cpufreq-dt: Correct i.MX8MP's market segment fuse location cpufreq: imx6q: read OCOTP through nvmem for imx6q cpufreq: imx6q: fix error handling cpufreq: imx-cpufreq-dt: Add "cpu-supply" property check cpufreq: ti-cpufreq: Add support for OPP_PLUS cpufreq: imx6q: Fixes unwanted cpu overclocking on i.MX6ULL
This commit is contained in:
Rafael J. Wysocki
Коммит
4d99175ab4
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@ -19,7 +19,8 @@ In 'cpu' nodes:
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In 'operating-points-v2' table:
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- compatible: Should be
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- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
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- 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
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apq8064, ipq8064, msm8960 and ipq8074.
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Optional properties:
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--------------------
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@ -128,7 +128,7 @@ config ARM_OMAP2PLUS_CPUFREQ
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config ARM_QCOM_CPUFREQ_NVMEM
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tristate "Qualcomm nvmem based CPUFreq"
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depends on ARM64
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depends on ARCH_QCOM
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depends on QCOM_QFPROM
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depends on QCOM_SMEM
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select PM_OPP
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@ -141,6 +141,11 @@ static const struct of_device_id blacklist[] __initconst = {
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{ .compatible = "ti,dra7", },
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{ .compatible = "ti,omap3", },
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{ .compatible = "qcom,ipq8064", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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{ .compatible = "qcom,msm8960", },
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{ }
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};
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@ -363,6 +363,10 @@ static int dt_cpufreq_probe(struct platform_device *pdev)
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dt_cpufreq_driver.resume = data->resume;
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if (data->suspend)
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dt_cpufreq_driver.suspend = data->suspend;
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if (data->get_intermediate) {
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dt_cpufreq_driver.target_intermediate = data->target_intermediate;
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dt_cpufreq_driver.get_intermediate = data->get_intermediate;
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}
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}
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ret = cpufreq_register_driver(&dt_cpufreq_driver);
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@ -14,6 +14,10 @@ struct cpufreq_policy;
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struct cpufreq_dt_platform_data {
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bool have_governor_per_policy;
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unsigned int (*get_intermediate)(struct cpufreq_policy *policy,
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unsigned int index);
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int (*target_intermediate)(struct cpufreq_policy *policy,
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unsigned int index);
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int (*suspend)(struct cpufreq_policy *policy);
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int (*resume)(struct cpufreq_policy *policy);
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};
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@ -19,6 +19,8 @@
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#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
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#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
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#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
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#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5
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#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5)
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/* cpufreq-dt device registered by imx-cpufreq-dt */
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static struct platform_device *cpufreq_dt_pdev;
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@ -31,6 +33,9 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
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int speed_grade, mkt_segment;
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int ret;
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if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL))
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return -ENODEV;
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ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
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if (ret)
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return ret;
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@ -42,7 +47,13 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
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else
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speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
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>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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if (of_machine_is_compatible("fsl,imx8mp"))
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mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)
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>> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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else
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mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)
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>> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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/*
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* Early samples without fuses written report "0 0" which may NOT
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@ -216,31 +216,41 @@ static struct cpufreq_driver imx6q_cpufreq_driver = {
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#define OCOTP_CFG3_SPEED_996MHZ 0x2
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#define OCOTP_CFG3_SPEED_852MHZ 0x1
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static void imx6q_opp_check_speed_grading(struct device *dev)
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static int imx6q_opp_check_speed_grading(struct device *dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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int ret;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np)
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return;
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if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
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ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
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if (ret)
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return ret;
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} else {
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np)
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return -ENOENT;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(dev, "failed to map ocotp\n");
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goto put_node;
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base = of_iomap(np, 0);
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of_node_put(np);
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if (!base) {
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dev_err(dev, "failed to map ocotp\n");
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return -EFAULT;
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}
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/*
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* SPEED_GRADING[1:0] defines the max speed of ARM:
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* 2b'11: 1200000000Hz;
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* 2b'10: 996000000Hz;
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* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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* 2b'00: 792000000Hz;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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iounmap(base);
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}
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/*
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* SPEED_GRADING[1:0] defines the max speed of ARM:
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* 2b'11: 1200000000Hz;
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* 2b'10: 996000000Hz;
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* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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* 2b'00: 792000000Hz;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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@ -257,9 +267,8 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
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if (dev_pm_opp_disable(dev, 1200000000))
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dev_warn(dev, "failed to disable 1.2GHz OPP\n");
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}
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iounmap(base);
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put_node:
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of_node_put(np);
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return 0;
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}
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#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
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@ -280,6 +289,9 @@ static int imx6ul_opp_check_speed_grading(struct device *dev)
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void __iomem *base;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
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if (!np)
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np = of_find_compatible_node(NULL, NULL,
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"fsl,imx6ull-ocotp");
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if (!np)
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return -ENOENT;
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@ -378,23 +390,22 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
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goto put_reg;
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}
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/* Because we have added the OPPs here, we must free them */
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free_opp = true;
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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ret = imx6ul_opp_check_speed_grading(cpu_dev);
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if (ret) {
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if (ret == -EPROBE_DEFER)
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goto put_node;
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} else {
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ret = imx6q_opp_check_speed_grading(cpu_dev);
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}
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if (ret) {
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if (ret != -EPROBE_DEFER)
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dev_err(cpu_dev, "failed to read ocotp: %d\n",
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ret);
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goto put_node;
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}
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} else {
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imx6q_opp_check_speed_grading(cpu_dev);
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goto out_free_opp;
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}
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/* Because we have added the OPPs here, we must free them */
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free_opp = true;
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num = dev_pm_opp_get_opp_count(cpu_dev);
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if (num < 0) {
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ret = num;
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@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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int (*get_version)(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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char **pvs_name,
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struct qcom_cpufreq_drv *drv);
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const char **genpd_names;
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};
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struct qcom_cpufreq_drv {
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struct opp_table **opp_tables;
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struct opp_table **names_opp_tables;
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struct opp_table **hw_opp_tables;
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struct opp_table **genpd_opp_tables;
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u32 versions;
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const struct qcom_cpufreq_match_data *data;
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@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
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static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
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static void get_krait_bin_format_a(struct device *cpu_dev,
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int *speed, int *pvs, int *pvs_ver,
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struct nvmem_cell *pvs_nvmem, u8 *buf)
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{
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u32 pte_efuse;
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pte_efuse = *((u32 *)buf);
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*speed = pte_efuse & 0xf;
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if (*speed == 0xf)
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*speed = (pte_efuse >> 4) & 0xf;
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if (*speed == 0xf) {
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*speed = 0;
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dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
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} else {
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dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
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}
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*pvs = (pte_efuse >> 10) & 0x7;
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if (*pvs == 0x7)
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*pvs = (pte_efuse >> 13) & 0x7;
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if (*pvs == 0x7) {
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*pvs = 0;
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dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
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} else {
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dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
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}
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}
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static void get_krait_bin_format_b(struct device *cpu_dev,
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int *speed, int *pvs, int *pvs_ver,
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struct nvmem_cell *pvs_nvmem, u8 *buf)
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{
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u32 pte_efuse, redundant_sel;
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pte_efuse = *((u32 *)buf);
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redundant_sel = (pte_efuse >> 24) & 0x7;
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*pvs_ver = (pte_efuse >> 4) & 0x3;
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switch (redundant_sel) {
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case 1:
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*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
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*speed = (pte_efuse >> 27) & 0xf;
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break;
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case 2:
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||||
*pvs = (pte_efuse >> 27) & 0xf;
|
||||
*speed = pte_efuse & 0x7;
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||||
break;
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||||
default:
|
||||
/* 4 bits of PVS are in efuse register bits 31, 8-6. */
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||||
*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
|
||||
*speed = pte_efuse & 0x7;
|
||||
}
|
||||
|
||||
/* Check SPEED_BIN_BLOW_STATUS */
|
||||
if (pte_efuse & BIT(3)) {
|
||||
dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
|
||||
} else {
|
||||
dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
|
||||
*speed = 0;
|
||||
}
|
||||
|
||||
/* Check PVS_BLOW_STATUS */
|
||||
pte_efuse = *(((u32 *)buf) + 4);
|
||||
pte_efuse &= BIT(21);
|
||||
if (pte_efuse) {
|
||||
dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
|
||||
} else {
|
||||
dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
|
||||
*pvs = 0;
|
||||
}
|
||||
|
||||
dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
|
||||
}
|
||||
|
||||
static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
|
||||
{
|
||||
size_t len;
|
||||
|
|
@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
|
|||
|
||||
static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
|
||||
struct nvmem_cell *speedbin_nvmem,
|
||||
char **pvs_name,
|
||||
struct qcom_cpufreq_drv *drv)
|
||||
{
|
||||
size_t len;
|
||||
u8 *speedbin;
|
||||
enum _msm8996_version msm8996_version;
|
||||
*pvs_name = NULL;
|
||||
|
||||
msm8996_version = qcom_cpufreq_get_msm_id();
|
||||
if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
|
||||
|
|
@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
|
||||
struct nvmem_cell *speedbin_nvmem,
|
||||
char **pvs_name,
|
||||
struct qcom_cpufreq_drv *drv)
|
||||
{
|
||||
int speed = 0, pvs = 0, pvs_ver = 0;
|
||||
u8 *speedbin;
|
||||
size_t len;
|
||||
|
||||
speedbin = nvmem_cell_read(speedbin_nvmem, &len);
|
||||
|
||||
if (IS_ERR(speedbin))
|
||||
return PTR_ERR(speedbin);
|
||||
|
||||
switch (len) {
|
||||
case 4:
|
||||
get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
|
||||
speedbin_nvmem, speedbin);
|
||||
break;
|
||||
case 8:
|
||||
get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
|
||||
speedbin_nvmem, speedbin);
|
||||
break;
|
||||
default:
|
||||
dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
|
||||
speed, pvs, pvs_ver);
|
||||
|
||||
drv->versions = (1 << speed);
|
||||
|
||||
kfree(speedbin);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct qcom_cpufreq_match_data match_data_kryo = {
|
||||
.get_version = qcom_cpufreq_kryo_name_version,
|
||||
};
|
||||
|
||||
static const struct qcom_cpufreq_match_data match_data_krait = {
|
||||
.get_version = qcom_cpufreq_krait_name_version,
|
||||
};
|
||||
|
||||
static const char *qcs404_genpd_names[] = { "cpr", NULL };
|
||||
|
||||
static const struct qcom_cpufreq_match_data match_data_qcs404 = {
|
||||
|
|
@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
|
|||
struct nvmem_cell *speedbin_nvmem;
|
||||
struct device_node *np;
|
||||
struct device *cpu_dev;
|
||||
char *pvs_name = "speedXX-pvsXX-vXX";
|
||||
unsigned cpu;
|
||||
const struct of_device_id *match;
|
||||
int ret;
|
||||
|
|
@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
|
|||
if (!np)
|
||||
return -ENOENT;
|
||||
|
||||
ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
|
||||
ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
|
||||
if (!ret) {
|
||||
of_node_put(np);
|
||||
return -ENOENT;
|
||||
|
|
@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
|
|||
goto free_drv;
|
||||
}
|
||||
|
||||
ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
|
||||
ret = drv->data->get_version(cpu_dev,
|
||||
speedbin_nvmem, &pvs_name, drv);
|
||||
if (ret) {
|
||||
nvmem_cell_put(speedbin_nvmem);
|
||||
goto free_drv;
|
||||
|
|
@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
|
|||
}
|
||||
of_node_put(np);
|
||||
|
||||
drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
|
||||
drv->names_opp_tables = kcalloc(num_possible_cpus(),
|
||||
sizeof(*drv->names_opp_tables),
|
||||
GFP_KERNEL);
|
||||
if (!drv->opp_tables) {
|
||||
if (!drv->names_opp_tables) {
|
||||
ret = -ENOMEM;
|
||||
goto free_drv;
|
||||
}
|
||||
drv->hw_opp_tables = kcalloc(num_possible_cpus(),
|
||||
sizeof(*drv->hw_opp_tables),
|
||||
GFP_KERNEL);
|
||||
if (!drv->hw_opp_tables) {
|
||||
ret = -ENOMEM;
|
||||
goto free_opp_names;
|
||||
}
|
||||
|
||||
drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
|
||||
sizeof(*drv->genpd_opp_tables),
|
||||
|
|
@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (drv->data->get_version) {
|
||||
drv->opp_tables[cpu] =
|
||||
dev_pm_opp_set_supported_hw(cpu_dev,
|
||||
&drv->versions, 1);
|
||||
if (IS_ERR(drv->opp_tables[cpu])) {
|
||||
ret = PTR_ERR(drv->opp_tables[cpu]);
|
||||
|
||||
if (pvs_name) {
|
||||
drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
|
||||
cpu_dev,
|
||||
pvs_name);
|
||||
if (IS_ERR(drv->names_opp_tables[cpu])) {
|
||||
ret = PTR_ERR(drv->names_opp_tables[cpu]);
|
||||
dev_err(cpu_dev, "Failed to add OPP name %s\n",
|
||||
pvs_name);
|
||||
goto free_opp;
|
||||
}
|
||||
}
|
||||
|
||||
drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
|
||||
cpu_dev, &drv->versions, 1);
|
||||
if (IS_ERR(drv->hw_opp_tables[cpu])) {
|
||||
ret = PTR_ERR(drv->hw_opp_tables[cpu]);
|
||||
dev_err(cpu_dev,
|
||||
"Failed to set supported hardware\n");
|
||||
goto free_genpd_opp;
|
||||
|
|
@ -259,11 +404,18 @@ free_genpd_opp:
|
|||
kfree(drv->genpd_opp_tables);
|
||||
free_opp:
|
||||
for_each_possible_cpu(cpu) {
|
||||
if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
|
||||
if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
|
||||
break;
|
||||
dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
|
||||
dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
|
||||
}
|
||||
kfree(drv->opp_tables);
|
||||
for_each_possible_cpu(cpu) {
|
||||
if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
|
||||
break;
|
||||
dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
|
||||
}
|
||||
kfree(drv->hw_opp_tables);
|
||||
free_opp_names:
|
||||
kfree(drv->names_opp_tables);
|
||||
free_drv:
|
||||
kfree(drv);
|
||||
|
||||
|
|
@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
|
|||
platform_device_unregister(cpufreq_dt_pdev);
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
if (drv->opp_tables[cpu])
|
||||
dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
|
||||
if (drv->names_opp_tables[cpu])
|
||||
dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
|
||||
if (drv->hw_opp_tables[cpu])
|
||||
dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
|
||||
if (drv->genpd_opp_tables[cpu])
|
||||
dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
|
||||
}
|
||||
|
||||
kfree(drv->opp_tables);
|
||||
kfree(drv->names_opp_tables);
|
||||
kfree(drv->hw_opp_tables);
|
||||
kfree(drv->genpd_opp_tables);
|
||||
kfree(drv);
|
||||
|
||||
|
|
@ -303,6 +458,10 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
|
|||
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
|
||||
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
|
||||
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
|
||||
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
|
||||
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,11 +25,14 @@
|
|||
|
||||
#define DRA7_EFUSE_HAS_OD_MPU_OPP 11
|
||||
#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
|
||||
#define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
|
||||
#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
|
||||
#define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
|
||||
|
||||
#define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
|
||||
#define DRA7_EFUSE_OD_MPU_OPP BIT(1)
|
||||
#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
|
||||
#define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
|
||||
|
||||
#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
|
||||
#define OMAP3_CONTROL_IDCODE 0x4830A204
|
||||
|
|
@ -80,6 +83,10 @@ static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
|
|||
*/
|
||||
|
||||
switch (efuse) {
|
||||
case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
|
||||
case DRA76_EFUSE_HAS_ALL_MPU_OPP:
|
||||
calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
|
||||
/* Fall through */
|
||||
case DRA7_EFUSE_HAS_ALL_MPU_OPP:
|
||||
case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
|
||||
calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
|
||||
|
|
|
|||
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