Memory controller drivers for v6.1 - Broadcom
Add support for the Broadcom STB memory controller (BRCMSTB_MEMC). -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmMbWlIQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD17jnD/9npugLq9QcT3et9bd8nS1IoX01Jyt/1/2X z5m9ns3kiGOpcDY48XfISg5LA99F4A63LT/04OKzL0DqAnPXQBj2Kzzq7dad+t6L iL6p+M5eYmVZg25aEaTykQ3axGEn0vKxY4HogKefu/+jDyNsXrKBtDbO7MHSmAdK FP8+3qj7bGehAU/jb4CV6SQmtJeb70nqz/vlo5o/ZjMXnDgHH0ygKaueOhEgFRp1 uwoSZohDNOhmEylzq+k4akiU7KxmobIDNd+jUxiaJDph92cHMHzzlKpWC0adEmfl +zbjRqPLQRnxbv1+4haFpnM8+Tnsxb3er+U1Lr+4pxFmaQ3xObOy3XvdUpxsNVFI bYKtMYnqnuLKZ6ciImAd64YgMcClQAsle2Dk4neCyPBobIHG4Twg9g1yh6N9dBtC EJjzTx9AaBipztzL3/3bGcXDvcuTxy/warg/A5O4UFuEPnmIPT7dwkmYX4sev5dN 3hyMAEQewRUa+KUu4xCqlixg/+Rk1s+V4GRpoFwYtXOeo7n4BSKBiYiJzdtm7J83 4SC15DIIJosrGo4bzbNFzZ2P7yeiYjqyLYzPDKu3eafe7TsrJ6jn/7WBJ279N43+ wvwhTS8q9f9TwEnnjkQ9WOrygUedJ/x7unbolNfSgWaX73SS/FH4B0pvYwbq0w01 FXy6DrEglg== =4VeH -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfSjYACgkQmmx57+YA GNm52Q//UlafPau8mcmYVoLzfTI2S5+PhmPW2U+n0//PMAkZvYNpb7zN7/EKppQ0 DNh4PLIO8kJBei7wkYw8Ur/fOt417JQ3sRzTGM+sdtV+zqBXY2Rd5sb3o+NrBMT8 T1YnaTkFQwVOJtxcp9Qzjnywxcd6i42uwewQNZ+YdqKCWNoNmo8G5fzdApAIrK1N nAbAVagj5zgq6W8IoIivE0ww75vV/PmiH2PhDFde96yl6oM1C+bkTTOYJv2p+trT /XVYk5jSPqKUHANj1uUvNZ8wJ+3SaXgTLu+qyN8yeip/kFjBvSyxS9VsXoDGS8V5 JZbGBmm2X5GMN06PYoboD7fQ5bOmSwiewFWDvOBLWYnXUqi1i3/F+AZAFCwoHMsM sT0IhnnXUkP8SlCtUe7U35Hqw7AipQOogYWAGCCNLxAYTYOSyqJWuffr0nWwDMQo 4/NY177friEny5O5TNlmuSMeo0Dl7TxDwUNugHdLnQSYdMjmU5MwNcBSbMlqVd/e Qat+0GvTW/T2NUEI2erE/6flX3X8km3f6UqzwOy5ytYxPAcqQ3r5K4l5aZBpQzEI tqoVvT/9W/1ptazS7uOzNAlCGZHkkWjdCLEWHsC3RoGvV5BdoZ/P9WJTzpXnGNt3 xjsFmKLa0v+H1RwOvS0Bk/t6wOm00tduHQ4gWLOHJ693Qaa7GQ0= =RC6E -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-brcm-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v6.1 - Broadcom Add support for the Broadcom STB memory controller (BRCMSTB_MEMC). * tag 'memory-controller-drv-brcm-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: brcmstb_memc: Add Broadcom STB memory controller driver Documentation: sysfs: Document Broadcom STB memc sysfs knobs dt-bindings: memory-controller: Document Broadcom STB MEMC Link: https://lore.kernel.org/r/20220909153037.824092-3-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
4da90678a6
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@ -0,0 +1,15 @@
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What: /sys/bus/platform/devices/*/srpd
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Date: July 2022
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KernelVersion: 5.21
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Contact: Florian Fainelli <f.fainelli@gmail.com>
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Description:
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Self Refresh Power Down (SRPD) inactivity timeout counted in
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internal DDR controller clock cycles. Possible values range
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from 0 (disable inactivity timeout) to 65535 (0xffff).
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What: /sys/bus/platform/devices/*/frequency
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Date: July 2022
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KernelVersion: 5.21
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Contact: Florian Fainelli <f.fainelli@gmail.com>
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Description:
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DDR PHY frequency in Hz.
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@ -187,15 +187,8 @@ Required properties:
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Sequencer DRAM parameters and control registers. Used for Self-Refresh
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Power-Down (SRPD), among other things.
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Required properties:
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- compatible : should contain one of these
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"brcm,brcmstb-memc-ddr-rev-b.2.1"
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"brcm,brcmstb-memc-ddr-rev-b.2.2"
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"brcm,brcmstb-memc-ddr-rev-b.2.3"
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"brcm,brcmstb-memc-ddr-rev-b.3.0"
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"brcm,brcmstb-memc-ddr-rev-b.3.1"
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"brcm,brcmstb-memc-ddr"
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- reg : the MEMC DDR register range
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See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
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full list of supported compatible strings and properties.
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Example:
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@ -0,0 +1,52 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Memory controller (MEMC) for Broadcom STB
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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properties:
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compatible:
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items:
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- enum:
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- brcm,brcmstb-memc-ddr-rev-b.1.x
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- brcm,brcmstb-memc-ddr-rev-b.2.0
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- brcm,brcmstb-memc-ddr-rev-b.2.1
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- brcm,brcmstb-memc-ddr-rev-b.2.2
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- brcm,brcmstb-memc-ddr-rev-b.2.3
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- brcm,brcmstb-memc-ddr-rev-b.2.5
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- brcm,brcmstb-memc-ddr-rev-b.2.6
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- brcm,brcmstb-memc-ddr-rev-b.2.7
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- brcm,brcmstb-memc-ddr-rev-b.2.8
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- brcm,brcmstb-memc-ddr-rev-b.3.0
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- brcm,brcmstb-memc-ddr-rev-b.3.1
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- brcm,brcmstb-memc-ddr-rev-c.1.0
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- brcm,brcmstb-memc-ddr-rev-c.1.1
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- brcm,brcmstb-memc-ddr-rev-c.1.2
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- brcm,brcmstb-memc-ddr-rev-c.1.3
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- brcm,brcmstb-memc-ddr-rev-c.1.4
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- const: brcm,brcmstb-memc-ddr
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reg:
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maxItems: 1
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clock-frequency:
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description: DDR PHY frequency in Hz
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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memory-controller@9902000 {
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compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";
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reg = <0x9902000 0x600>;
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clock-frequency = <2133000000>;
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};
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@ -66,6 +66,15 @@ config BRCMSTB_DPFE
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for the DRAM's temperature. Slower refresh rate means cooler RAM,
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higher refresh rate means hotter RAM.
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config BRCMSTB_MEMC
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tristate "Broadcom STB MEMC driver"
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default ARCH_BRCMSTB
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depends on ARCH_BRCMSTB || COMPILE_TEST
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help
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This driver provides a way to configure the Broadcom STB memory
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controller and specifically control the Self Refresh Power Down
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(SRPD) inactivity timeout.
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config BT1_L2_CTL
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bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
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depends on MIPS_BAIKAL_T1 || COMPILE_TEST
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@ -11,6 +11,7 @@ obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o
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obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
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obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o
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obj-$(CONFIG_BRCMSTB_DPFE) += brcmstb_dpfe.o
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obj-$(CONFIG_BRCMSTB_MEMC) += brcmstb_memc.o
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obj-$(CONFIG_BT1_L2_CTL) += bt1-l2-ctl.o
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obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
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obj-$(CONFIG_TI_EMIF) += emif.o
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@ -0,0 +1,301 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#define REG_MEMC_CNTRLR_CONFIG 0x00
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#define CNTRLR_CONFIG_LPDDR4_SHIFT 5
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#define CNTRLR_CONFIG_MASK 0xf
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#define REG_MEMC_SRPD_CFG_21 0x20
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#define REG_MEMC_SRPD_CFG_20 0x34
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#define REG_MEMC_SRPD_CFG_1x 0x3c
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#define INACT_COUNT_SHIFT 0
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#define INACT_COUNT_MASK 0xffff
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#define SRPD_EN_SHIFT 16
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struct brcmstb_memc_data {
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u32 srpd_offset;
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};
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struct brcmstb_memc {
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struct device *dev;
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void __iomem *ddr_ctrl;
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unsigned int timeout_cycles;
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u32 frequency;
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u32 srpd_offset;
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};
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static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc)
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{
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void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG;
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u32 reg;
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reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK;
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return reg == CNTRLR_CONFIG_LPDDR4_SHIFT;
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}
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static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
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unsigned int cycles)
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{
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void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
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u32 val;
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/* Max timeout supported in HW */
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if (cycles > INACT_COUNT_MASK)
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return -EINVAL;
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memc->timeout_cycles = cycles;
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val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK;
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if (cycles)
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val |= BIT(SRPD_EN_SHIFT);
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writel_relaxed(val, cfg);
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/* Ensure the write is committed to the controller */
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(void)readl_relaxed(cfg);
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return 0;
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}
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static ssize_t frequency_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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return sprintf(buf, "%d\n", memc->frequency);
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}
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static ssize_t srpd_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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return sprintf(buf, "%d\n", memc->timeout_cycles);
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}
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static ssize_t srpd_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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unsigned int val;
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int ret;
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/*
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* Cannot change the inactivity timeout on LPDDR4 chips because the
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* dynamic tuning process will also get affected by the inactivity
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* timeout, thus making it non functional.
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*/
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if (brcmstb_memc_uses_lpddr4(memc))
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return -EOPNOTSUPP;
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ret = kstrtouint(buf, 10, &val);
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if (ret < 0)
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return ret;
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ret = brcmstb_memc_srpd_config(memc, val);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RO(frequency);
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static DEVICE_ATTR_RW(srpd);
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static struct attribute *dev_attrs[] = {
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&dev_attr_frequency.attr,
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&dev_attr_srpd.attr,
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NULL,
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};
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static struct attribute_group dev_attr_group = {
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.attrs = dev_attrs,
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};
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static const struct of_device_id brcmstb_memc_of_match[];
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static int brcmstb_memc_probe(struct platform_device *pdev)
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{
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const struct brcmstb_memc_data *memc_data;
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const struct of_device_id *of_id;
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struct device *dev = &pdev->dev;
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struct brcmstb_memc *memc;
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int ret;
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memc = devm_kzalloc(dev, sizeof(*memc), GFP_KERNEL);
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if (!memc)
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return -ENOMEM;
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dev_set_drvdata(dev, memc);
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of_id = of_match_device(brcmstb_memc_of_match, dev);
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memc_data = of_id->data;
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memc->srpd_offset = memc_data->srpd_offset;
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memc->ddr_ctrl = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(memc->ddr_ctrl))
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return PTR_ERR(memc->ddr_ctrl);
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of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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&memc->frequency);
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ret = sysfs_create_group(&dev->kobj, &dev_attr_group);
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if (ret)
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return ret;
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return 0;
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}
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static int brcmstb_memc_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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sysfs_remove_group(&dev->kobj, &dev_attr_group);
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return 0;
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}
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enum brcmstb_memc_hwtype {
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BRCMSTB_MEMC_V21,
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BRCMSTB_MEMC_V20,
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BRCMSTB_MEMC_V1X,
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};
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static const struct brcmstb_memc_data brcmstb_memc_versions[] = {
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{ .srpd_offset = REG_MEMC_SRPD_CFG_21 },
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{ .srpd_offset = REG_MEMC_SRPD_CFG_20 },
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{ .srpd_offset = REG_MEMC_SRPD_CFG_1x },
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};
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static const struct of_device_id brcmstb_memc_of_match[] = {
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V20]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.2",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.3",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
|
||||
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.4",
|
||||
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
|
||||
},
|
||||
/* default to the original offset */
|
||||
{
|
||||
.compatible = "brcm,brcmstb-memc-ddr",
|
||||
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static int brcmstb_memc_suspend(struct device *dev)
|
||||
{
|
||||
struct brcmstb_memc *memc = dev_get_drvdata(dev);
|
||||
void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
|
||||
u32 val;
|
||||
|
||||
if (memc->timeout_cycles == 0)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Disable SRPD prior to suspending the system since that can
|
||||
* cause issues with other memory clients managed by the ARM
|
||||
* trusted firmware to access memory.
|
||||
*/
|
||||
val = readl_relaxed(cfg);
|
||||
val &= ~BIT(SRPD_EN_SHIFT);
|
||||
writel_relaxed(val, cfg);
|
||||
/* Ensure the write is committed to the controller */
|
||||
(void)readl_relaxed(cfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcmstb_memc_resume(struct device *dev)
|
||||
{
|
||||
struct brcmstb_memc *memc = dev_get_drvdata(dev);
|
||||
|
||||
if (memc->timeout_cycles == 0)
|
||||
return 0;
|
||||
|
||||
return brcmstb_memc_srpd_config(memc, memc->timeout_cycles);
|
||||
}
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_memc_pm_ops, brcmstb_memc_suspend,
|
||||
brcmstb_memc_resume);
|
||||
|
||||
static struct platform_driver brcmstb_memc_driver = {
|
||||
.probe = brcmstb_memc_probe,
|
||||
.remove = brcmstb_memc_remove,
|
||||
.driver = {
|
||||
.name = "brcmstb_memc",
|
||||
.of_match_table = brcmstb_memc_of_match,
|
||||
.pm = pm_ptr(&brcmstb_memc_pm_ops),
|
||||
},
|
||||
};
|
||||
module_platform_driver(brcmstb_memc_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Broadcom");
|
||||
MODULE_DESCRIPTION("DDR SRPD driver for Broadcom STB chips");
|
||||
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