mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit
Most registers need to wait until the command is completed, not necessarily until the bus is free. At least, R-Car 2+ SoCs can signal that via the CBSY bit, so let's use it there instead of SCLKDIVEN to save a little bit of delay. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Родитель
01ffb1ae84
Коммит
4dc48a95fa
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@ -398,12 +398,14 @@ static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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}
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static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
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static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
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{
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int timeout = 1000;
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/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
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u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
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while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
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& TMIO_STAT_SCLKDIVEN))
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while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
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& bit) == wait_state)
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udelay(1);
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if (!timeout) {
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@ -416,17 +418,22 @@ static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
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static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
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{
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u32 bit = TMIO_STAT_SCLKDIVEN;
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switch (addr) {
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case CTL_SD_CMD:
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case CTL_STOP_INTERNAL_ACTION:
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case CTL_XFER_BLK_COUNT:
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case CTL_SD_CARD_CLK_CTL:
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case CTL_SD_XFER_LEN:
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case CTL_SD_MEM_CARD_OPT:
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case CTL_TRANSACTION_CTL:
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case CTL_DMA_ENABLE:
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case EXT_ACC:
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return renesas_sdhi_wait_idle(host);
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if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
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bit = TMIO_STAT_CMD_BUSY;
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/* fallthrough */
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case CTL_SD_CARD_CLK_CTL:
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return renesas_sdhi_wait_idle(host, bit);
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}
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return 0;
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