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perf vendor events: Update metrics for Haswell 

Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are updated to version 30:
    https://download.01.org/perfmon/HSW
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

Not tested on a Haswell, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-15-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-01-31 17:58:46 -08:00 коммит произвёл Arnaldo Carvalho de Melo
Родитель 45957c1e23
Коммит 4dd252721b
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1824
tools/perf/pmu-events/arch/x86/haswell/cache.json
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167
tools/perf/pmu-events/arch/x86/haswell/floating-point.json
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[
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xC1",
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC6",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
"SampleAfterValue": "2000003",
"UMask": "0x7"
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
"SampleAfterValue": "100003",
"UMask": "0x1e"
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xC1",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"UMask": "0x10",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
"EventCode": "0xC6",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "AVX_INSTS.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "SSE* FP micro-code assist when output value is invalid.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Any input SSE* FP Assist",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "1",
"PublicDescription": "",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x1e",
"EventName": "FP_ASSIST.ANY",
"SampleAfterValue": "100003",
"BriefDescription": "Counts any FP_ASSIST umask was incrementing",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x10"
}
]

576
tools/perf/pmu-events/arch/x86/haswell/frontend.json
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@ -1,294 +1,304 @@
[
{
"PublicDescription": "Counts cycles the IDQ is empty.",
"EventCode": "0x79",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"Errata": "HSD135",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"CounterHTOff": "0,1,2,3"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
"SampleAfterValue": "100003",
"UMask": "0x1f"
},
{
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
"EventCode": "0x79",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EdgeDetect": "1",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x18",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x18",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x24",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x24",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering any Uop",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EdgeDetect": "1",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Number of uops delivered to IDQ from any path.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x3c",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ICACHE.IFETCH_STALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"CounterHTOff": "0,1,2,3"
},
{
"PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.",
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"CounterMask": "3",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Errata": "HSD135",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "Counts cycles the IDQ is empty.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
"SampleAfterValue": "2000003",
"UMask": "0x3c"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]

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tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
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[
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Frontend_Bound",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
},
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Frontend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Bad_Speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Bad_Speculation_SMT",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
"MetricGroup": "TopdownL1",
"MetricName": "Backend_Bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Backend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. "
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Retiring_SMT",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1",
"MetricGroup": "Ret;Summary",
"MetricName": "IPC"
},
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Retire",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI"
},
{
"BriefDescription": "Instruction per taken branch",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fetch_BW;PGO",
"MetricName": "IpTB"
},
{
"BriefDescription": "Branch instructions per taken branch. ",
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;PGO",
"MetricName": "BpTB"
},
{
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions",
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
"MetricGroup": "PGO;IcMiss",
"MetricName": "IFetch_Line_Utilization"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fetch_BW",
"MetricName": "DSB_Coverage"
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "UpTB"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
"MetricGroup": "Pipeline;Summary",
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "Pipeline;Mem",
"MetricName": "CPI"
},
{
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"MetricGroup": "Pipeline",
"MetricName": "CLKS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * cycles",
"MetricGroup": "TopDownL1",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TmaL1",
"MetricName": "SLOTS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopDownL1_SMT",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "TmaL1_SMT",
"MetricName": "SLOTS_SMT"
},
{
"BriefDescription": "Instructions per Load (lower number means higher occurance rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricGroup": "Instruction_Type",
"MetricName": "IpL"
},
{
"BriefDescription": "Instructions per Store (lower number means higher occurance rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
"MetricGroup": "Instruction_Type",
"MetricName": "IpS"
},
{
"BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"MetricGroup": "Branches;Instruction_Type",
"MetricName": "IpB"
},
{
"BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
"MetricGroup": "Branches",
"MetricName": "IpCall"
},
{
"BriefDescription": "Total number of retired Instructions",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary",
"MetricName": "Instructions"
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / cycles",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;SMT;TmaL1",
"MetricName": "CoreIPC"
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;SMT;TmaL1_SMT",
"MetricName": "CoreIPC_SMT"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
"MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
"MetricGroup": "Pipeline",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "BrMispredicts",
"MetricGroup": "Bad;BadSpec;BrMispredicts",
"MetricName": "IpMispredict"
},
{
@ -176,83 +129,127 @@
"MetricName": "CORE_CLKS"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
"BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricGroup": "InsType",
"MetricName": "IpLoad"
},
{
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
"MetricGroup": "InsType",
"MetricName": "IpStore"
},
{
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"MetricGroup": "Branches;Fed;InsType",
"MetricName": "IpBranch"
},
{
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
"MetricGroup": "Branches;Fed;PGO",
"MetricName": "IpCall"
},
{
"BriefDescription": "Instruction per taken branch",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
"MetricName": "IpTB"
},
{
"BriefDescription": "Branch instructions per taken branch. ",
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;PGO",
"MetricName": "BpTkBranch"
},
{
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary;TmaL1",
"MetricName": "Instructions"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
"MetricGroup": "Memory_Bound;Memory_Lat",
"MetricName": "Load_Miss_Real_Latency"
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency",
"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
},
{
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
"MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
"MetricGroup": "Memory_Bound;Memory_BW",
"MetricGroup": "Mem;MemoryBound;MemoryBW",
"MetricName": "MLP"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles",
"MetricGroup": "TLB",
"MetricName": "Page_Walks_Utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TLB_SMT",
"MetricName": "Page_Walks_Utilization_SMT"
},
{
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"MetricGroup": "Memory_BW",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"MetricGroup": "Memory_BW",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"MetricGroup": "Memory_BW",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "Cache_Misses",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Cache_Misses",
"MetricGroup": "Mem;Backend;CacheMisses",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Cache_Misses",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Cache_Misses",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "Cache_Misses",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "Page_Walks_Utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Mem;MemoryTLB_SMT",
"MetricName": "Page_Walks_Utilization_SMT"
},
{
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricGroup": "Summary",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
"MetricGroup": "Summary;Power",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Average Frequency Utilization relative nominal frequency",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC",
@ -261,22 +258,46 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT;Summary",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
{
"BriefDescription": "Fraction of cycles spent in Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS",
"MetricName": "Kernel_Utilization"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
"MetricGroup": "OS",
"MetricName": "Kernel_CPI"
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
"MetricGroup": "Memory_BW",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{
"BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",

1110
tools/perf/pmu-events/arch/x86/haswell/memory.json
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52
tools/perf/pmu-events/arch/x86/haswell/other.json
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@ -1,43 +1,43 @@
[
{
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"EventCode": "0x5C",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100003",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
"EventCode": "0x63",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]

2452
tools/perf/pmu-events/arch/x86/haswell/pipeline.json
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tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json Normal file
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[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"UMask": "0x46",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"UMask": "0x4f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop hits a modified line in some processor core.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"UMask": "0x84",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"UMask": "0x24",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"PublicDescription": "An external snoop misses in some processor core.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
]

69
tools/perf/pmu-events/arch/x86/haswell/uncore-other.json Normal file
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[
{
"BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
"EventCode": "0x83",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
"PerPkg": "1",
"PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Unit": "NCU"
}
]

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tools/perf/pmu-events/arch/x86/haswell/uncore.json
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[
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x21",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"BriefDescription": "An external snoop misses in some processor core.",
"PublicDescription": "An external snoop misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x41",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x81",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x24",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
"PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x44",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x84",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x28",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"BriefDescription": "An external snoop hits a modified line in some processor core.",
"PublicDescription": "An external snoop hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x48",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x88",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x11",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x21",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x41",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x81",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x18",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x28",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
"PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x48",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x88",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x1f",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x2f",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x4f",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x8f",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x86",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x46",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x16",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x26",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x81",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x81",
"UMask": "0x20",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x83",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
"BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
"PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x84",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "NCU",
"EventCode": "0x0",
"UMask": "0x01",
"EventName": "UNC_CLOCK.SOCKET",
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "FIXED",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
}
]

672
tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
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[
{
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
"EventCode": "0x08",
"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
"SampleAfterValue": "2000003",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x60"
},
{
"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
"EventCode": "0x08",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "2000003",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x40"
},
{
"EventCode": "0x08",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
"Counter": "0,1,2,3",
"UMask": "0x8",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "2000003",
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
"EventCode": "0x08",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3",
"UMask": "0xe",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"SampleAfterValue": "2000003",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Number of cache load STLB hits. No page walk.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"SampleAfterValue": "100003",
"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
"EventCode": "0x49",
"BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x80"
},
{
"EventCode": "0x49",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"UMask": "0x8",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"UMask": "0x60"
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
"EventCode": "0x49",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3",
"UMask": "0xe",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
"EventCode": "0x49",
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"EventCode": "0x49",
"BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"SampleAfterValue": "100003",
"BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycle count for an Extended Page table walk.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
"EventCode": "0x85",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
"SampleAfterValue": "100003",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
"EventCode": "0x85",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
"SampleAfterValue": "100003",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x60"
},
{
"EventCode": "0x85",
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
"Counter": "0,1,2,3",
"UMask": "0x8",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"PublicDescription": "ITLB misses that hit STLB (2M).",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"PublicDescription": "ITLB misses that hit STLB (4K).",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x8"
},
{
"PublicDescription": "Completed page walks in ITLB of any page size.",
"EventCode": "0x85",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"UMask": "0xe",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x4"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
"EventCode": "0x85",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "ITLB_MISSES.WALK_DURATION",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "ITLB misses that hit STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
"SampleAfterValue": "100003",
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"PublicDescription": "ITLB misses that hit STLB (2M).",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x60",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
"EventCode": "0xae",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100003",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x11",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in the L1+FB",
"CounterHTOff": "0,1,2,3"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
"SampleAfterValue": "2000003",
"UMask": "0x11"
},
{
"PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x12",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in the L2",
"CounterHTOff": "0,1,2,3"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
"SampleAfterValue": "2000003",
"UMask": "0x12"
},
{
"PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x14",
"Errata": "HSD25",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
"CounterHTOff": "0,1,2,3"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
"PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
"SampleAfterValue": "2000003",
"UMask": "0x14"
},
{
"PublicDescription": "Number of DTLB page walker loads from memory.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x18",
"Errata": "HSD25",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of DTLB page walker hits in Memory",
"CounterHTOff": "0,1,2,3"
},
{
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x21",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
"CounterHTOff": "0,1,2,3"
},
{
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x22",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L2",
"CounterHTOff": "0,1,2,3"
},
{
"PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x24",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
"PublicDescription": "Number of DTLB page walker loads from memory.",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
"CounterHTOff": "0,1,2,3"
"UMask": "0x18"
},
{
"PublicDescription": "Number of ITLB page walker loads from memory.",
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"UMask": "0x28",
"Errata": "HSD25",
"EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of ITLB page walker hits in Memory",
"CounterHTOff": "0,1,2,3"
},
{
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"Counter": "0,1,2,3",
"UMask": "0x41",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x41"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
"Counter": "0,1,2,3",
"UMask": "0x42",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x42"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
"Counter": "0,1,2,3",
"UMask": "0x44",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x44"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
"Counter": "0,1,2,3",
"UMask": "0x48",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x48"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"UMask": "0x81",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x81"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"UMask": "0x82",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x82"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"UMask": "0x84",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x84"
},
{
"EventCode": "0xBC",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
"Counter": "0,1,2,3",
"UMask": "0x88",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x88"
},
{
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
"EventCode": "0xBD",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
"SampleAfterValue": "2000003",
"UMask": "0x21"
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
"SampleAfterValue": "2000003",
"UMask": "0x22"
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Number of ITLB page walker hits in Memory",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
"PublicDescription": "Number of ITLB page walker loads from memory.",
"SampleAfterValue": "2000003",
"UMask": "0x28"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"PublicDescription": "Count number of STLB flush attempts.",
"EventCode": "0xBD",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100003",
"BriefDescription": "STLB flush attempts",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
"SampleAfterValue": "100003",
"UMask": "0x20"
}
]