KVM: nVMX: clean up posted interrupt descriptor try_cmpxchg
Rely on try_cmpxchg64 for re-reading the PID on failure, using READ_ONCE only right before the first iteration. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Родитель
4b88b1a518
Коммит
4de5c54f8c
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@ -34,7 +34,7 @@ static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
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return &(to_vmx(vcpu)->pi_desc);
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}
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static int pi_try_set_control(struct pi_desc *pi_desc, u64 old, u64 new)
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static int pi_try_set_control(struct pi_desc *pi_desc, u64 *pold, u64 new)
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{
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/*
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* PID.ON can be set at any time by a different vCPU or by hardware,
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@ -42,7 +42,7 @@ static int pi_try_set_control(struct pi_desc *pi_desc, u64 old, u64 new)
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* update must be retried with a fresh snapshot an ON change causes
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* the cmpxchg to fail.
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*/
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if (!try_cmpxchg64(&pi_desc->control, &old, new))
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if (!try_cmpxchg64(&pi_desc->control, pold, new))
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return -EBUSY;
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return 0;
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@ -96,8 +96,9 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
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if (!x2apic_mode)
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dest = (dest << 8) & 0xFF00;
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old.control = READ_ONCE(pi_desc->control);
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do {
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old.control = new.control = READ_ONCE(pi_desc->control);
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new.control = old.control;
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/*
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* Clear SN (as above) and refresh the destination APIC ID to
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@ -111,7 +112,7 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
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* descriptor was modified on "put" to use the wakeup vector.
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*/
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new.nv = POSTED_INTR_VECTOR;
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} while (pi_try_set_control(pi_desc, old.control, new.control));
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} while (pi_try_set_control(pi_desc, &old.control, new.control));
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local_irq_restore(flags);
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@ -156,12 +157,12 @@ static void pi_enable_wakeup_handler(struct kvm_vcpu *vcpu)
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WARN(pi_desc->sn, "PI descriptor SN field set before blocking");
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old.control = READ_ONCE(pi_desc->control);
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do {
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old.control = new.control = READ_ONCE(pi_desc->control);
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/* set 'NV' to 'wakeup vector' */
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new.control = old.control;
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new.nv = POSTED_INTR_WAKEUP_VECTOR;
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} while (pi_try_set_control(pi_desc, old.control, new.control));
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} while (pi_try_set_control(pi_desc, &old.control, new.control));
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/*
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* Send a wakeup IPI to this CPU if an interrupt may have been posted
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