omap3: nand: prefetch in irq mode support
This patch enable prefetch-irq mode for nand transfer(read, write) Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Sukumar Ghorai
Tony Lindgren
Родитель
db97eb7dfe
Коммит
4e07037616
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@ -16,6 +16,7 @@
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/io.h>
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#include <plat/irqs.h>
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#include <plat/gpmc.h>
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#include <plat/nand.h>
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@ -147,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
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board_nand_data.nr_parts = nr_parts;
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board_nand_data.devsize = nand_type;
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board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
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gpmc_nand_init(&board_nand_data);
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}
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#else
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@ -13,7 +13,8 @@
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enum nand_io {
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NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
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NAND_OMAP_POLLED, /* polled mode, without prefetch */
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NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */
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NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
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NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
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};
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struct omap_nand_platform_data {
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@ -26,6 +27,7 @@ struct omap_nand_platform_data {
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int (*nand_setup)(void);
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int (*dev_ready)(struct omap_nand_platform_data *);
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int dma_channel;
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int gpmc_irq;
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enum nand_io xfer_type;
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unsigned long phys_base;
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int devsize;
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@ -11,6 +11,7 @@
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include <linux/mtd/mtd.h>
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@ -24,6 +25,7 @@
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#include <plat/nand.h>
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#define DRIVER_NAME "omap2-nand"
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#define OMAP_NAND_TIMEOUT_MS 5000
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#define NAND_Ecc_P1e (1 << 0)
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#define NAND_Ecc_P2e (1 << 1)
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@ -108,6 +110,13 @@ struct omap_nand_info {
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unsigned long phys_base;
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struct completion comp;
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int dma_ch;
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int gpmc_irq;
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enum {
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OMAP_NAND_IO_READ = 0, /* read */
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OMAP_NAND_IO_WRITE, /* write */
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} iomode;
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u_char *buf;
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int buf_len;
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};
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/**
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@ -267,9 +276,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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uint32_t pref_count = 0, w_count = 0;
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uint32_t w_count = 0;
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int i = 0, ret = 0;
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u16 *p;
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unsigned long tim, limit;
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/* take care of subpage writes */
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if (len % 2 != 0) {
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@ -295,9 +305,12 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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iowrite16(*p++, info->nand.IO_ADDR_W);
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}
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/* wait for data to flushed-out before reset the prefetch */
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do {
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pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT);
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} while (pref_count);
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tim = 0;
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limit = (loops_per_jiffy *
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msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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cpu_relax();
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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}
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@ -326,11 +339,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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uint32_t prefetch_status = 0;
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enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
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DMA_FROM_DEVICE;
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dma_addr_t dma_addr;
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int ret;
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unsigned long tim, limit;
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/* The fifo depth is 64 bytes. We have a sync at each frame and frame
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* length is 64 bytes.
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@ -376,7 +389,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
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if (ret)
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/* PFPW engine is busy, use cpu copy methode */
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy;
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init_completion(&info->comp);
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@ -385,10 +398,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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/* setup and start DMA using dma_addr */
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wait_for_completion(&info->comp);
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tim = 0;
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limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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cpu_relax();
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do {
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prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
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} while (prefetch_status);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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@ -436,6 +450,155 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd,
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omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
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}
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/*
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* omap_nand_irq - GMPC irq handler
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* @this_irq: gpmc irq number
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* @dev: omap_nand_info structure pointer is passed here
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*/
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static irqreturn_t omap_nand_irq(int this_irq, void *dev)
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{
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struct omap_nand_info *info = (struct omap_nand_info *) dev;
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u32 bytes;
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u32 irq_stat;
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irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
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bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
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bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
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if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
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if (irq_stat & 0x2)
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goto done;
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if (info->buf_len && (info->buf_len < bytes))
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bytes = info->buf_len;
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else if (!info->buf_len)
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bytes = 0;
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iowrite32_rep(info->nand.IO_ADDR_W,
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(u32 *)info->buf, bytes >> 2);
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info->buf = info->buf + bytes;
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info->buf_len -= bytes;
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} else {
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ioread32_rep(info->nand.IO_ADDR_R,
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(u32 *)info->buf, bytes >> 2);
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info->buf = info->buf + bytes;
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if (irq_stat & 0x2)
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goto done;
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}
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gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
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return IRQ_HANDLED;
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done:
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complete(&info->comp);
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/* disable irq */
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gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
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/* clear status */
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gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
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return IRQ_HANDLED;
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}
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/*
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* omap_read_buf_irq_pref - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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int ret = 0;
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if (len <= mtd->oobsize) {
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omap_read_buf_pref(mtd, buf, len);
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return;
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}
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info->iomode = OMAP_NAND_IO_READ;
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info->buf = buf;
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init_completion(&info->comp);
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
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if (ret)
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy;
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info->buf_len = len;
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/* enable irq */
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gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
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(GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
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/* waiting for read to complete */
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wait_for_completion(&info->comp);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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return;
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out_copy:
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if (info->nand.options & NAND_BUSWIDTH_16)
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omap_read_buf16(mtd, buf, len);
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else
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omap_read_buf8(mtd, buf, len);
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}
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/*
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* omap_write_buf_irq_pref - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void omap_write_buf_irq_pref(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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int ret = 0;
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unsigned long tim, limit;
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if (len <= mtd->oobsize) {
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omap_write_buf_pref(mtd, buf, len);
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return;
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}
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info->iomode = OMAP_NAND_IO_WRITE;
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info->buf = (u_char *) buf;
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init_completion(&info->comp);
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
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if (ret)
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy;
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info->buf_len = len;
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/* enable irq */
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gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
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(GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
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/* waiting for write to complete */
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wait_for_completion(&info->comp);
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/* wait for data to flushed-out before reset the prefetch */
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tim = 0;
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limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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cpu_relax();
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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return;
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out_copy:
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if (info->nand.options & NAND_BUSWIDTH_16)
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omap_write_buf16(mtd, buf, len);
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else
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omap_write_buf8(mtd, buf, len);
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}
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/**
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* omap_verify_buf - Verify chip data against buffer
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* @mtd: MTD device structure
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@ -846,6 +1009,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
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}
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break;
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case NAND_OMAP_PREFETCH_IRQ:
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err = request_irq(pdata->gpmc_irq,
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omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
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if (err) {
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dev_err(&pdev->dev, "requesting irq(%d) error:%d",
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pdata->gpmc_irq, err);
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goto out_release_mem_region;
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} else {
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info->gpmc_irq = pdata->gpmc_irq;
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info->nand.read_buf = omap_read_buf_irq_pref;
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info->nand.write_buf = omap_write_buf_irq_pref;
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}
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break;
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default:
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dev_err(&pdev->dev,
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"xfer_type(%d) not supported!\n", pdata->xfer_type);
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@ -911,6 +1088,9 @@ static int omap_nand_remove(struct platform_device *pdev)
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if (info->dma_ch != -1)
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omap_free_dma(info->dma_ch);
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if (info->gpmc_irq)
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free_irq(info->gpmc_irq, info);
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/* Release NAND device, its internal structures and partitions */
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nand_release(&info->mtd);
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iounmap(info->nand.IO_ADDR_R);
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