iio: adc: rockchip_saradc: Add support iio buffers
Add the ability to also support access via (triggered) buffers next to the existing direct mode. Device in question is the Odroid Go Advance that connects a joystick to two of the saradc channels for X and Y axis and the new (and still pending) adc joystick driver of course wants to use triggered buffers from the iio subsystem. Signed-off-by: Simon Xue <xxm@rock-chips.com> [some simplifications and added commit description] Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Simon Xue
Jonathan Cameron
Родитель
71eb7c855b
Коммит
4e130dc7b4
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@ -15,7 +15,10 @@
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define SARADC_DATA 0x00
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@ -32,9 +35,9 @@
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#define SARADC_DLY_PU_SOC_MASK 0x3f
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#define SARADC_TIMEOUT msecs_to_jiffies(100)
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#define SARADC_MAX_CHANNELS 6
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struct rockchip_saradc_data {
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int num_bits;
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const struct iio_chan_spec *channels;
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int num_channels;
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unsigned long clk_rate;
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@ -49,8 +52,37 @@ struct rockchip_saradc {
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struct reset_control *reset;
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const struct rockchip_saradc_data *data;
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u16 last_val;
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const struct iio_chan_spec *last_chan;
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};
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static void rockchip_saradc_power_down(struct rockchip_saradc *info)
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{
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/* Clear irq & power down adc */
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writel_relaxed(0, info->regs + SARADC_CTRL);
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}
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static int rockchip_saradc_conversion(struct rockchip_saradc *info,
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struct iio_chan_spec const *chan)
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{
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reinit_completion(&info->completion);
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/* 8 clock periods as delay between power up and start cmd */
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writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
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info->last_chan = chan;
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/* Select the channel to be used and trigger conversion */
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writel(SARADC_CTRL_POWER_CTRL
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| (chan->channel & SARADC_CTRL_CHN_MASK)
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| SARADC_CTRL_IRQ_ENABLE,
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info->regs + SARADC_CTRL);
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if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
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return -ETIMEDOUT;
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return 0;
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}
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static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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@ -62,22 +94,11 @@ static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&indio_dev->mlock);
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reinit_completion(&info->completion);
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/* 8 clock periods as delay between power up and start cmd */
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writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
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/* Select the channel to be used and trigger conversion */
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writel(SARADC_CTRL_POWER_CTRL
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| (chan->channel & SARADC_CTRL_CHN_MASK)
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| SARADC_CTRL_IRQ_ENABLE,
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info->regs + SARADC_CTRL);
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if (!wait_for_completion_timeout(&info->completion,
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SARADC_TIMEOUT)) {
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writel_relaxed(0, info->regs + SARADC_CTRL);
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ret = rockchip_saradc_conversion(info, chan);
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if (ret) {
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rockchip_saradc_power_down(info);
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mutex_unlock(&indio_dev->mlock);
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return -ETIMEDOUT;
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return ret;
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}
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*val = info->last_val;
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@ -91,7 +112,7 @@ static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
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}
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*val = ret / 1000;
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*val2 = info->data->num_bits;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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@ -104,10 +125,9 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
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/* Read value */
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info->last_val = readl_relaxed(info->regs + SARADC_DATA);
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info->last_val &= GENMASK(info->data->num_bits - 1, 0);
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info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
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/* Clear irq & power down adc */
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writel_relaxed(0, info->regs + SARADC_CTRL);
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rockchip_saradc_power_down(info);
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complete(&info->completion);
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@ -118,51 +138,55 @@ static const struct iio_info rockchip_saradc_iio_info = {
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.read_raw = rockchip_saradc_read_raw,
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};
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#define SARADC_CHANNEL(_index, _id) { \
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#define SARADC_CHANNEL(_index, _id, _res) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = _id, \
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.scan_index = _index, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = _res, \
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.storagebits = 16, \
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.endianness = IIO_CPU, \
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}, \
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}
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static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0"),
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SARADC_CHANNEL(1, "adc1"),
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SARADC_CHANNEL(2, "adc2"),
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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};
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static const struct rockchip_saradc_data saradc_data = {
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.num_bits = 10,
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.channels = rockchip_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
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.clk_rate = 1000000,
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};
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static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0"),
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SARADC_CHANNEL(1, "adc1"),
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SARADC_CHANNEL(0, "adc0", 12),
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SARADC_CHANNEL(1, "adc1", 12),
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};
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static const struct rockchip_saradc_data rk3066_tsadc_data = {
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.num_bits = 12,
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.channels = rockchip_rk3066_tsadc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
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.clk_rate = 50000,
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};
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static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0"),
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SARADC_CHANNEL(1, "adc1"),
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SARADC_CHANNEL(2, "adc2"),
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SARADC_CHANNEL(3, "adc3"),
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SARADC_CHANNEL(4, "adc4"),
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SARADC_CHANNEL(5, "adc5"),
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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SARADC_CHANNEL(3, "adc3", 10),
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SARADC_CHANNEL(4, "adc4", 10),
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SARADC_CHANNEL(5, "adc5", 10),
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};
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static const struct rockchip_saradc_data rk3399_saradc_data = {
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.num_bits = 10,
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.channels = rockchip_rk3399_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
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.clk_rate = 1000000,
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@ -214,6 +238,46 @@ static void rockchip_saradc_regulator_disable(void *data)
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regulator_disable(info->vref);
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}
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static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *i_dev = pf->indio_dev;
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struct rockchip_saradc *info = iio_priv(i_dev);
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/*
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* @values: each channel takes an u16 value
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* @timestamp: will be 8-byte aligned automatically
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*/
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struct {
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u16 values[SARADC_MAX_CHANNELS];
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int64_t timestamp;
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} data;
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int ret;
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int i, j = 0;
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mutex_lock(&i_dev->mlock);
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for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
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const struct iio_chan_spec *chan = &i_dev->channels[i];
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ret = rockchip_saradc_conversion(info, chan);
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if (ret) {
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rockchip_saradc_power_down(info);
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goto out;
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}
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data.values[j] = info->last_val;
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j++;
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}
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iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
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out:
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mutex_unlock(&i_dev->mlock);
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iio_trigger_notify_done(i_dev->trig);
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return IRQ_HANDLED;
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}
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static int rockchip_saradc_probe(struct platform_device *pdev)
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{
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struct rockchip_saradc *info = NULL;
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@ -242,6 +306,12 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
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info->data = match->data;
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/* Sanity check for possible later IP variants with more channels */
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if (info->data->num_channels > SARADC_MAX_CHANNELS) {
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dev_err(&pdev->dev, "max channels exceeded");
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return -EINVAL;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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info->regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(info->regs))
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@ -354,6 +424,11 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
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indio_dev->channels = info->data->channels;
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indio_dev->num_channels = info->data->num_channels;
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ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
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rockchip_saradc_trigger_handler,
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NULL);
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if (ret)
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return ret;
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return devm_iio_device_register(&pdev->dev, indio_dev);
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}
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