gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()
Add register offsets for GPIO_IRQSTATUS_RAW_0, GPIO_IRQSTATUS_RAW_0 which are present on OMAP4+ processors. Now we can distinguish conditions applicable to OMAP4,5 and those specific to OMAP24xx and OMAP3xxx. Cc: Kevin Hilman <khilman@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Cousson, Benoit <b-cousson@ti.com> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Govindraj.R <govindraj.raja@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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@ -101,6 +101,8 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
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pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
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pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
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pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
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pdata->regs->irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0;
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pdata->regs->irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1;
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pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
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pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
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pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
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@ -172,6 +172,8 @@ struct omap_gpio_reg_offs {
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u16 clr_dataout;
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u16 irqstatus;
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u16 irqstatus2;
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u16 irqstatus_raw0;
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u16 irqstatus_raw1;
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u16 irqenable;
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u16 irqenable2;
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u16 set_irqenable;
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@ -1286,14 +1286,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
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old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
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old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
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if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
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if (!bank->regs->irqstatus_raw0) {
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__raw_writel(old0 | gen, bank->base +
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bank->regs->leveldetect0);
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__raw_writel(old1 | gen, bank->base +
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bank->regs->leveldetect1);
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}
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if (cpu_is_omap44xx()) {
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if (bank->regs->irqstatus_raw0) {
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__raw_writel(old0 | l, bank->base +
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bank->regs->leveldetect0);
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__raw_writel(old1 | l, bank->base +
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