x86/asm/tsc: Rename native_read_tsc() to rdtsc()
Now that there is no paravirt TSC, the "native" is inappropriate. The function does RDTSC, so give it the obvious name: rdtsc(). Suggested-by: Borislav Petkov <bp@suse.de> Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Len Brown <lenb@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kvm ML <kvm@vger.kernel.org> Link: http://lkml.kernel.org/r/fd43e16281991f096c1e4d21574d9e1402c62d39.1434501121.git.luto@kernel.org [ Ported it to v4.2-rc1. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
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fe47ae6e1a
Коммит
4ea1636b04
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@ -82,7 +82,7 @@ static unsigned long get_random_long(void)
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if (has_cpuflag(X86_FEATURE_TSC)) {
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debug_putstr(" RDTSC");
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raw = native_read_tsc();
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raw = rdtsc();
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random ^= raw;
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use_i8254 = false;
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@ -186,7 +186,7 @@ notrace static cycle_t vread_tsc(void)
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* but no one has ever seen it happen.
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*/
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rdtsc_barrier();
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ret = (cycle_t)native_read_tsc();
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ret = (cycle_t)rdtsc();
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last = gtod->cycle_last;
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@ -109,7 +109,16 @@ notrace static inline int native_write_msr_safe(unsigned int msr,
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int wrmsr_safe_regs(u32 regs[8]);
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static __always_inline unsigned long long native_read_tsc(void)
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/**
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* rdtsc() - returns the current TSC without ordering constraints
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*
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* rdtsc() returns the result of RDTSC as a 64-bit integer. The
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* only ordering constraint it supplies is the ordering implied by
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* "asm volatile": it will put the RDTSC in the place you expect. The
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* CPU can and will speculatively execute that RDTSC, though, so the
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* results can be non-monotonic if compared on different CPUs.
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*/
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static __always_inline unsigned long long rdtsc(void)
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{
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DECLARE_ARGS(val, low, high);
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@ -62,7 +62,7 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift)
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static __always_inline
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u64 pvclock_get_nsec_offset(const struct pvclock_vcpu_time_info *src)
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{
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u64 delta = native_read_tsc() - src->tsc_timestamp;
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u64 delta = rdtsc() - src->tsc_timestamp;
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return pvclock_scale_delta(delta, src->tsc_to_system_mul,
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src->tsc_shift);
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}
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@ -72,7 +72,7 @@ static __always_inline void boot_init_stack_canary(void)
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* on during the bootup the random pool has true entropy too.
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*/
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get_random_bytes(&canary, sizeof(canary));
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tsc = native_read_tsc();
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tsc = rdtsc();
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canary += tsc + (tsc << 32UL);
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current->stack_canary = canary;
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@ -26,7 +26,7 @@ static inline cycles_t get_cycles(void)
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return 0;
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#endif
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return native_read_tsc();
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return rdtsc();
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}
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extern void tsc_init(void);
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@ -263,7 +263,7 @@ static int apbt_clocksource_register(void)
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/* Verify whether apbt counter works */
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t1 = dw_apb_clocksource_read(clocksource_apbt);
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start = native_read_tsc();
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start = rdtsc();
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/*
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* We don't know the TSC frequency yet, but waiting for
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@ -273,7 +273,7 @@ static int apbt_clocksource_register(void)
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*/
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do {
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rep_nop();
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now = native_read_tsc();
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now = rdtsc();
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} while ((now - start) < 200000UL);
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/* APBT is the only always on clocksource, it has to work! */
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@ -390,13 +390,13 @@ unsigned long apbt_quick_calibrate(void)
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old = dw_apb_clocksource_read(clocksource_apbt);
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old += loop;
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t1 = native_read_tsc();
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t1 = rdtsc();
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do {
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new = dw_apb_clocksource_read(clocksource_apbt);
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} while (new < old);
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t2 = native_read_tsc();
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t2 = rdtsc();
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shift = 5;
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if (unlikely(loop >> shift == 0)) {
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@ -457,7 +457,7 @@ static int lapic_next_deadline(unsigned long delta,
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{
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u64 tsc;
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tsc = native_read_tsc();
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tsc = rdtsc();
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wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
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return 0;
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}
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@ -592,7 +592,7 @@ static void __init lapic_cal_handler(struct clock_event_device *dev)
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unsigned long pm = acpi_pm_read_early();
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if (cpu_has_tsc)
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tsc = native_read_tsc();
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tsc = rdtsc();
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switch (lapic_cal_loops++) {
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case 0:
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@ -1209,7 +1209,7 @@ void setup_local_APIC(void)
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long long max_loops = cpu_khz ? cpu_khz : 1000000;
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if (cpu_has_tsc)
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tsc = native_read_tsc();
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tsc = rdtsc();
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if (disable_apic) {
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disable_ioapic_support();
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@ -1293,7 +1293,7 @@ void setup_local_APIC(void)
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}
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if (queued) {
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if (cpu_has_tsc && cpu_khz) {
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ntsc = native_read_tsc();
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ntsc = rdtsc();
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max_loops = (cpu_khz << 10) - (ntsc - tsc);
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} else
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max_loops--;
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@ -125,10 +125,10 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
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n = K6_BUG_LOOP;
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f_vide = vide;
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d = native_read_tsc();
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d = rdtsc();
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while (n--)
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f_vide();
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d2 = native_read_tsc();
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d2 = rdtsc();
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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@ -125,7 +125,7 @@ void mce_setup(struct mce *m)
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{
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memset(m, 0, sizeof(struct mce));
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m->cpu = m->extcpu = smp_processor_id();
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m->tsc = native_read_tsc();
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m->tsc = rdtsc();
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/* We hope get_seconds stays lockless */
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m->time = get_seconds();
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m->cpuvendor = boot_cpu_data.x86_vendor;
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@ -1784,7 +1784,7 @@ static void collect_tscs(void *data)
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{
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unsigned long *cpu_tsc = (unsigned long *)data;
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cpu_tsc[smp_processor_id()] = native_read_tsc();
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cpu_tsc[smp_processor_id()] = rdtsc();
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}
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static int mce_apei_read_done;
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@ -110,7 +110,7 @@ static void init_espfix_random(void)
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*/
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if (!arch_get_random_long(&rand)) {
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/* The constant is an arbitrary large prime */
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rand = native_read_tsc();
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rand = rdtsc();
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rand *= 0xc345c6b72fd16123UL;
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}
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@ -735,7 +735,7 @@ static int hpet_clocksource_register(void)
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/* Verify whether hpet counter works */
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t1 = hpet_readl(HPET_COUNTER);
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start = native_read_tsc();
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start = rdtsc();
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/*
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* We don't know the TSC frequency yet, but waiting for
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@ -745,7 +745,7 @@ static int hpet_clocksource_register(void)
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*/
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do {
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rep_nop();
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now = native_read_tsc();
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now = rdtsc();
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} while ((now - start) < 200000UL);
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if (t1 == hpet_readl(HPET_COUNTER)) {
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@ -15,7 +15,7 @@ u64 notrace trace_clock_x86_tsc(void)
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u64 ret;
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rdtsc_barrier();
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ret = native_read_tsc();
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ret = rdtsc();
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return ret;
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}
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@ -248,7 +248,7 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
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data = cyc2ns_write_begin(cpu);
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tsc_now = native_read_tsc();
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tsc_now = rdtsc();
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ns_now = cycles_2_ns(tsc_now);
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/*
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@ -290,7 +290,7 @@ u64 native_sched_clock(void)
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}
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/* read the Time Stamp Counter: */
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tsc_now = native_read_tsc();
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tsc_now = rdtsc();
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/* return the value in ns */
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return cycles_2_ns(tsc_now);
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@ -1172,7 +1172,7 @@ void wait_lapic_expire(struct kvm_vcpu *vcpu)
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tsc_deadline = apic->lapic_timer.expired_tscdeadline;
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apic->lapic_timer.expired_tscdeadline = 0;
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guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
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guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
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trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
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/* __delay is delay_tsc whenever the hardware has TSC, thus always. */
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@ -1240,7 +1240,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
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local_irq_save(flags);
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now = apic->lapic_timer.timer.base->get_time();
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guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
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guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
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if (likely(tscdeadline > guest_tsc)) {
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ns = (tscdeadline - guest_tsc) * 1000000ULL;
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do_div(ns, this_tsc_khz);
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@ -1080,7 +1080,7 @@ static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
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{
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u64 tsc;
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tsc = svm_scale_tsc(vcpu, native_read_tsc());
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tsc = svm_scale_tsc(vcpu, rdtsc());
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return target_tsc - tsc;
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}
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@ -3079,7 +3079,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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switch (msr_info->index) {
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case MSR_IA32_TSC: {
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msr_info->data = svm->vmcb->control.tsc_offset +
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svm_scale_tsc(vcpu, native_read_tsc());
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svm_scale_tsc(vcpu, rdtsc());
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break;
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}
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@ -2236,7 +2236,7 @@ static u64 guest_read_tsc(void)
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{
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u64 host_tsc, tsc_offset;
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host_tsc = native_read_tsc();
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host_tsc = rdtsc();
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tsc_offset = vmcs_read64(TSC_OFFSET);
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return host_tsc + tsc_offset;
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}
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@ -2317,7 +2317,7 @@ static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool ho
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static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
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{
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return target_tsc - native_read_tsc();
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return target_tsc - rdtsc();
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}
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static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
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@ -1455,7 +1455,7 @@ static cycle_t read_tsc(void)
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* but no one has ever seen it happen.
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*/
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rdtsc_barrier();
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ret = (cycle_t)native_read_tsc();
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ret = (cycle_t)rdtsc();
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last = pvclock_gtod_data.clock.cycle_last;
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@ -1646,7 +1646,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
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return 1;
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}
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if (!use_master_clock) {
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host_tsc = native_read_tsc();
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host_tsc = rdtsc();
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kernel_ns = get_kernel_ns();
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}
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@ -2810,7 +2810,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
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s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
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native_read_tsc() - vcpu->arch.last_host_tsc;
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rdtsc() - vcpu->arch.last_host_tsc;
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if (tsc_delta < 0)
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mark_tsc_unstable("KVM discovered backwards TSC");
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if (check_tsc_unstable()) {
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@ -2838,7 +2838,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
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{
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kvm_x86_ops->vcpu_put(vcpu);
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kvm_put_guest_fpu(vcpu);
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vcpu->arch.last_host_tsc = native_read_tsc();
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vcpu->arch.last_host_tsc = rdtsc();
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}
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static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
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@ -6623,7 +6623,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
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hw_breakpoint_restore();
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vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
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native_read_tsc());
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rdtsc());
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vcpu->mode = OUTSIDE_GUEST_MODE;
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smp_wmb();
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@ -7437,7 +7437,7 @@ int kvm_arch_hardware_enable(void)
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if (ret != 0)
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return ret;
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local_tsc = native_read_tsc();
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local_tsc = rdtsc();
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stable = !check_tsc_unstable();
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list_for_each_entry(kvm, &vm_list, vm_list) {
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kvm_for_each_vcpu(i, vcpu, kvm) {
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@ -55,10 +55,10 @@ static void delay_tsc(unsigned long __loops)
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preempt_disable();
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cpu = smp_processor_id();
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rdtsc_barrier();
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bclock = native_read_tsc();
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bclock = rdtsc();
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for (;;) {
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rdtsc_barrier();
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now = native_read_tsc();
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now = rdtsc();
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if ((now - bclock) >= loops)
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break;
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@ -80,7 +80,7 @@ static void delay_tsc(unsigned long __loops)
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loops -= (now - bclock);
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cpu = smp_processor_id();
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rdtsc_barrier();
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bclock = native_read_tsc();
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bclock = rdtsc();
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}
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}
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preempt_enable();
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@ -100,7 +100,7 @@ void use_tsc_delay(void)
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int read_current_timer(unsigned long *timer_val)
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{
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if (delay_fn == delay_tsc) {
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*timer_val = native_read_tsc();
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*timer_val = rdtsc();
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return 0;
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}
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return -1;
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@ -765,7 +765,7 @@ static inline void intel_pstate_sample(struct cpudata *cpu)
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local_irq_save(flags);
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rdmsrl(MSR_IA32_APERF, aperf);
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rdmsrl(MSR_IA32_MPERF, mperf);
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tsc = native_read_tsc();
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tsc = rdtsc();
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local_irq_restore(flags);
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cpu->last_sample_time = cpu->sample.time;
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@ -149,9 +149,9 @@ static int old_gameport_measure_speed(struct gameport *gameport)
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for(i = 0; i < 50; i++) {
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local_irq_save(flags);
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t1 = native_read_tsc();
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t1 = rdtsc();
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for (t = 0; t < 50; t++) gameport_read(gameport);
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t2 = native_read_tsc();
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t2 = rdtsc();
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local_irq_restore(flags);
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udelay(i * 10);
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if (t2 - t1 < tx) tx = t2 - t1;
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@ -143,7 +143,7 @@ struct analog_port {
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#include <linux/i8253.h>
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#define GET_TIME(x) do { if (cpu_has_tsc) x = (unsigned int)native_read_tsc(); else x = get_time_pit(); } while (0)
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#define GET_TIME(x) do { if (cpu_has_tsc) x = (unsigned int)rdtsc(); else x = get_time_pit(); } while (0)
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#define DELTA(x,y) (cpu_has_tsc ? ((y) - (x)) : ((x) - (y) + ((x) < (y) ? PIT_TICK_RATE / HZ : 0)))
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#define TIME_NAME (cpu_has_tsc?"TSC":"PIT")
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static unsigned int get_time_pit(void)
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|
@ -160,7 +160,7 @@ static unsigned int get_time_pit(void)
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return count;
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||||
}
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||||
#elif defined(__x86_64__)
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||||
#define GET_TIME(x) do { x = (unsigned int)native_read_tsc(); } while (0)
|
||||
#define GET_TIME(x) do { x = (unsigned int)rdtsc(); } while (0)
|
||||
#define DELTA(x,y) ((y)-(x))
|
||||
#define TIME_NAME "TSC"
|
||||
#elif defined(__alpha__) || defined(CONFIG_MN10300) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_TILE)
|
||||
|
|
|
@ -638,7 +638,7 @@ static int receive(struct net_device *dev, int cnt)
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|||
#define GETTICK(x) \
|
||||
({ \
|
||||
if (cpu_has_tsc) \
|
||||
x = (unsigned int)native_read_tsc(); \
|
||||
x = (unsigned int)rdtsc(); \
|
||||
})
|
||||
#else /* __i386__ */
|
||||
#define GETTICK(x)
|
||||
|
|
|
@ -340,7 +340,7 @@ static bool powerclamp_adjust_controls(unsigned int target_ratio,
|
|||
|
||||
/* check result for the last window */
|
||||
msr_now = pkg_state_counter();
|
||||
tsc_now = native_read_tsc();
|
||||
tsc_now = rdtsc();
|
||||
|
||||
/* calculate pkg cstate vs tsc ratio */
|
||||
if (!msr_last || !tsc_last)
|
||||
|
@ -482,7 +482,7 @@ static void poll_pkg_cstate(struct work_struct *dummy)
|
|||
u64 val64;
|
||||
|
||||
msr_now = pkg_state_counter();
|
||||
tsc_now = native_read_tsc();
|
||||
tsc_now = rdtsc();
|
||||
jiffies_now = jiffies;
|
||||
|
||||
/* calculate pkg cstate vs tsc ratio */
|
||||
|
|
|
@ -81,11 +81,11 @@ static int __init cpufreq_test_tsc(void)
|
|||
|
||||
printk(KERN_DEBUG "start--> \n");
|
||||
then = read_pmtmr();
|
||||
then_tsc = native_read_tsc();
|
||||
then_tsc = rdtsc();
|
||||
for (i=0;i<20;i++) {
|
||||
mdelay(100);
|
||||
now = read_pmtmr();
|
||||
now_tsc = native_read_tsc();
|
||||
now_tsc = rdtsc();
|
||||
diff = (now - then) & 0xFFFFFF;
|
||||
diff_tsc = now_tsc - then_tsc;
|
||||
printk(KERN_DEBUG "t1: %08u t2: %08u diff_pmtmr: %08u diff_tsc: %016llu\n", then, now, diff, diff_tsc);
|
||||
|
|
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