drm/radeon/kms: clean up atombios pll code
- split pll adjust into a separate function - use a union for SetPixelClock params Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
Родитель
fc10332b8a
Коммит
4eaeca3351
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@ -409,30 +409,22 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
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}
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}
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void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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union adjust_pixel_clock {
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ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
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};
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static u32 atombios_adjust_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct radeon_pll *pll)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder = NULL;
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struct radeon_encoder *radeon_encoder = NULL;
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uint8_t frev, crev;
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int index;
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SET_PIXEL_CLOCK_PS_ALLOCATION args;
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PIXEL_CLOCK_PARAMETERS *spc1_ptr;
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PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
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PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
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uint32_t pll_clock = mode->clock;
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uint32_t adjusted_clock;
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uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
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struct radeon_pll *pll;
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u32 adjusted_clock = mode->clock;
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if (radeon_crtc->crtc_id == 0)
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pll = &rdev->clock.p1pll;
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else
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pll = &rdev->clock.p2pll;
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memset(&args, 0, sizeof(args));
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/* reset the pll flags */
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pll->flags = 0;
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if (ASIC_IS_AVIVO(rdev)) {
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if ((rdev->family == CHIP_RS600) ||
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@ -457,15 +449,17 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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if (!ASIC_IS_AVIVO(rdev)) {
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if (encoder->encoder_type !=
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DRM_MODE_ENCODER_DAC)
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radeon_encoder = to_radeon_encoder(encoder);
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if (ASIC_IS_AVIVO(rdev)) {
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/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
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if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
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adjusted_clock = mode->clock * 2;
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} else {
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if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
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pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
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if (encoder->encoder_type ==
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DRM_MODE_ENCODER_LVDS)
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if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
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pll->flags |= RADEON_PLL_USE_REF_DIV;
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}
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radeon_encoder = to_radeon_encoder(encoder);
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break;
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}
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}
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@ -475,28 +469,88 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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* special hw requirements.
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*/
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if (ASIC_IS_DCE3(rdev)) {
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ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
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union adjust_pixel_clock args;
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struct radeon_encoder_atom_dig *dig;
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u8 frev, crev;
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int index;
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if (!encoder)
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return;
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memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
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adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
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adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
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adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
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if (!radeon_encoder->enc_priv)
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return adjusted_clock;
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dig = radeon_encoder->enc_priv;
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index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
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atom_execute_table(rdev->mode_info.atom_context,
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index, (uint32_t *)&adjust_pll_args);
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adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
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} else {
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/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
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if (ASIC_IS_AVIVO(rdev) &&
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(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
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adjusted_clock = mode->clock * 2;
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else
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adjusted_clock = mode->clock;
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atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
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&crev);
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memset(&args, 0, sizeof(args));
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switch (frev) {
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case 1:
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switch (crev) {
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case 1:
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case 2:
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args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v1.ucTransmitterID = radeon_encoder->encoder_id;
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args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
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atom_execute_table(rdev->mode_info.atom_context,
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index, (uint32_t *)&args);
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adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return adjusted_clock;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return adjusted_clock;
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}
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}
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return adjusted_clock;
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}
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union set_pixel_clock {
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SET_PIXEL_CLOCK_PS_ALLOCATION base;
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PIXEL_CLOCK_PARAMETERS v1;
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PIXEL_CLOCK_PARAMETERS_V2 v2;
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PIXEL_CLOCK_PARAMETERS_V3 v3;
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};
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void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder = NULL;
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struct radeon_encoder *radeon_encoder = NULL;
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u8 frev, crev;
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int index;
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union set_pixel_clock args;
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u32 pll_clock = mode->clock;
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u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
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struct radeon_pll *pll;
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u32 adjusted_clock;
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memset(&args, 0, sizeof(args));
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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radeon_encoder = to_radeon_encoder(encoder);
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break;
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}
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}
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if (!radeon_encoder)
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return;
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if (radeon_crtc->crtc_id == 0)
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pll = &rdev->clock.p1pll;
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else
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pll = &rdev->clock.p2pll;
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/* adjust pixel clock as needed */
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adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
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if (ASIC_IS_AVIVO(rdev)) {
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if (radeon_new_pll)
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@ -519,45 +573,38 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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case 1:
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switch (crev) {
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case 1:
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spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
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spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
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spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc1_ptr->ucFracFbDiv = frac_fb_div;
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spc1_ptr->ucPostDiv = post_div;
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spc1_ptr->ucPpll =
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args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v1.usRefDiv = cpu_to_le16(ref_div);
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args.v1.usFbDiv = cpu_to_le16(fb_div);
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args.v1.ucFracFbDiv = frac_fb_div;
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args.v1.ucPostDiv = post_div;
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args.v1.ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
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spc1_ptr->ucRefDivSrc = 1;
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args.v1.ucCRTC = radeon_crtc->crtc_id;
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args.v1.ucRefDivSrc = 1;
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break;
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case 2:
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spc2_ptr =
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(PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
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spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
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spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc2_ptr->ucFracFbDiv = frac_fb_div;
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spc2_ptr->ucPostDiv = post_div;
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spc2_ptr->ucPpll =
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args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v2.usRefDiv = cpu_to_le16(ref_div);
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args.v2.usFbDiv = cpu_to_le16(fb_div);
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args.v2.ucFracFbDiv = frac_fb_div;
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args.v2.ucPostDiv = post_div;
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args.v2.ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
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spc2_ptr->ucRefDivSrc = 1;
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args.v2.ucCRTC = radeon_crtc->crtc_id;
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args.v2.ucRefDivSrc = 1;
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break;
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case 3:
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if (!encoder)
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return;
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spc3_ptr =
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(PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
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spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
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spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc3_ptr->ucFracFbDiv = frac_fb_div;
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spc3_ptr->ucPostDiv = post_div;
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spc3_ptr->ucPpll =
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args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v3.usRefDiv = cpu_to_le16(ref_div);
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args.v3.usFbDiv = cpu_to_le16(fb_div);
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args.v3.ucFracFbDiv = frac_fb_div;
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args.v3.ucPostDiv = post_div;
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args.v3.ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
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spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
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spc3_ptr->ucEncoderMode =
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args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
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args.v3.ucTransmitterId = radeon_encoder->encoder_id;
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args.v3.ucEncoderMode =
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atombios_get_encoder_mode(encoder);
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break;
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default:
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@ -570,7 +617,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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return;
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}
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printk("executing set pll\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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