Merge branch 'pci/host-hisi' into next
* pci/host-hisi: PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver
This commit is contained in:
Bjorn Helgaas
Коммит
4ed31f24a6
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@ -166,6 +166,23 @@ Example:
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reboot-offset = <0x4>;
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};
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-----------------------------------------------------------------------
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Hisilicon HiP05 PCIe-SAS system controller
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Required properties:
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- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
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- reg : Register address and size
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The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
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HiP05 Soc to implement some basic configurations.
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Example:
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/* for HiP05 PCIe-SAS system */
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pcie_sas: system_controller@0xb0000000 {
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compatible = "hisilicon,pcie-sas-subctrl", "syscon";
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reg = <0xb0000000 0x10000>;
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};
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-----------------------------------------------------------------------
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Hisilicon CPU controller
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@ -0,0 +1,44 @@
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HiSilicon PCIe host bridge DT description
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HiSilicon PCIe host controller is based on Designware PCI core.
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It shares common functions with PCIe Designware core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt.
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Additional properties are described here:
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Required properties:
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- compatible: Should contain "hisilicon,hip05-pcie".
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- reg: Should contain rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"rc_dbi": controller configuration registers;
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"config": PCIe configuration space registers.
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- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
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- port-id: Should be 0, 1, 2 or 3.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if DMA operations are coherent.
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Example:
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pcie@0xb0080000 {
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compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
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reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
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reg-names = "rc_dbi", "config";
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bus-range = <0 15>;
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msi-parent = <&its_pcie>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
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num-lanes = <8>;
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port-id = <1>;
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#interrupts-cells = <1>;
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interrupts-map-mask = <0xf800 0 0 7>;
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interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
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0x0 0 0 2 &mbigen_pcie 2 11
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0x0 0 0 3 &mbigen_pcie 3 12
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0x0 0 0 4 &mbigen_pcie 4 13>;
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status = "ok";
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};
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@ -8063,6 +8063,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
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F: drivers/pci/host/pci-xgene-msi.c
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PCIE DRIVER FOR HISILICON
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M: Zhou Wang <wangzhou1@hisilicon.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
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F: drivers/pci/host/pcie-hisi.c
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PCMCIA SUBSYSTEM
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P: Linux PCMCIA Team
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L: linux-pcmcia@lists.infradead.org
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@ -164,4 +164,12 @@ config PCIE_ALTERA_MSI
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Say Y here if you want PCIe MSI support for the Altera FPGA.
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This MSI driver supports Altera MSI to GIC controller IP.
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config PCI_HISI
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depends on OF && ARM64
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bool "HiSilicon SoC HIP05 PCIe controller"
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select PCIEPORTBUS
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select PCIE_DW
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help
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Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
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endmenu
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@ -19,3 +19,4 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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@ -0,0 +1,198 @@
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/*
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* PCIe host controller driver for HiSilicon Hip05 SoC
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*
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* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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* Author: Zhou Wang <wangzhou1@hisilicon.com>
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* Dacai Zhu <zhudacai@hisilicon.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
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#define PCIE_LTSSM_LINKUP_STATE 0x11
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#define PCIE_LTSSM_STATE_MASK 0x3F
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#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
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struct hisi_pcie {
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struct regmap *subctrl;
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void __iomem *reg_base;
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u32 port_id;
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struct pcie_port pp;
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};
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static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
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u32 val, u32 reg)
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{
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writel(val, pcie->reg_base + reg);
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}
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static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
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{
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return readl(pcie->reg_base + reg);
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}
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/* Hip05 PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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u32 reg;
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u32 reg_val;
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struct hisi_pcie *pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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if (size == 1)
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*val = *(u8 __force *) walker;
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else if (size == 2)
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*val = *(u16 __force *) walker;
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else if (size != 4)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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/* Hip05 PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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u32 reg_val;
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u32 reg;
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struct hisi_pcie *pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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if (size == 4)
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hisi_pcie_apb_writel(pcie, val, reg);
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else if (size == 2) {
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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*(u16 __force *) walker = val;
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hisi_pcie_apb_writel(pcie, reg_val, reg);
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} else if (size == 1) {
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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*(u8 __force *) walker = val;
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hisi_pcie_apb_writel(pcie, reg_val, reg);
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} else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static int hisi_pcie_link_up(struct pcie_port *pp)
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{
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u32 val;
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
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0x100 * hisi_pcie->port_id, &val);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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static struct pcie_host_ops hisi_pcie_host_ops = {
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.rd_own_conf = hisi_pcie_cfg_read,
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.wr_own_conf = hisi_pcie_cfg_write,
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.link_up = hisi_pcie_link_up,
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};
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static int __init hisi_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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u32 port_id;
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) {
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dev_err(&pdev->dev, "failed to read port-id\n");
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return -EINVAL;
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}
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if (port_id > 3) {
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dev_err(&pdev->dev, "Invalid port-id: %d\n", port_id);
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return -EINVAL;
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}
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hisi_pcie->port_id = port_id;
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pp->ops = &hisi_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init hisi_pcie_probe(struct platform_device *pdev)
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{
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struct hisi_pcie *hisi_pcie;
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struct pcie_port *pp;
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struct resource *reg;
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int ret;
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hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
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if (!hisi_pcie)
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return -ENOMEM;
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pp = &hisi_pcie->pp;
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pp->dev = &pdev->dev;
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hisi_pcie->subctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
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if (IS_ERR(hisi_pcie->subctrl)) {
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dev_err(pp->dev, "cannot get subctrl base\n");
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return PTR_ERR(hisi_pcie->subctrl);
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}
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reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
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hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg);
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if (IS_ERR(hisi_pcie->reg_base)) {
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dev_err(pp->dev, "cannot get rc_dbi base\n");
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return PTR_ERR(hisi_pcie->reg_base);
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}
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hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
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ret = hisi_add_pcie_port(pp, pdev);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, hisi_pcie);
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dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
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return 0;
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}
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static const struct of_device_id hisi_pcie_of_match[] = {
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{.compatible = "hisilicon,hip05-pcie",},
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{},
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};
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MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
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static struct platform_driver hisi_pcie_driver = {
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.probe = hisi_pcie_probe,
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.driver = {
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.name = "hisi-pcie",
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.of_match_table = hisi_pcie_of_match,
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},
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};
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module_platform_driver(hisi_pcie_driver);
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