ASoC: McASP: add support for clock dividers
Add support for the internal clock dividers of the McASP driver. Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Коммит
4ed8c9b737
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@ -199,6 +199,7 @@
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#define ACLKXE BIT(5)
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#define ACLKXE BIT(5)
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#define TX_ASYNC BIT(6)
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#define TX_ASYNC BIT(6)
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#define ACLKXPOL BIT(7)
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#define ACLKXPOL BIT(7)
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#define ACLKXDIV_MASK 0x1f
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/*
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/*
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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@ -207,6 +208,7 @@
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#define ACLKRE BIT(5)
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#define ACLKRE BIT(5)
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#define RX_ASYNC BIT(6)
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#define RX_ASYNC BIT(6)
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#define ACLKRPOL BIT(7)
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#define ACLKRPOL BIT(7)
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#define ACLKRDIV_MASK 0x1f
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/*
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/*
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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@ -215,6 +217,7 @@
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#define AHCLKXDIV(val) (val)
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#define AHCLKXDIV(val) (val)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXE BIT(15)
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#define AHCLKXE BIT(15)
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#define AHCLKXDIV_MASK 0xfff
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/*
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/*
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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@ -223,6 +226,7 @@
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#define AHCLKRDIV(val) (val)
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#define AHCLKRDIV(val) (val)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRE BIT(15)
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#define AHCLKRE BIT(15)
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#define AHCLKRDIV_MASK 0xfff
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/*
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/*
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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@ -554,6 +558,32 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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return 0;
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return 0;
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}
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}
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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
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{
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struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
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switch (div_id) {
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case 0: /* MCLK divider */
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
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AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
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AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
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break;
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case 1: /* BCLK divider */
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
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ACLKXDIV(div - 1), ACLKXDIV_MASK);
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
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ACLKRDIV(div - 1), ACLKRDIV_MASK);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int davinci_config_channel_size(struct davinci_audio_dev *dev,
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static int davinci_config_channel_size(struct davinci_audio_dev *dev,
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int channel_size)
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int channel_size)
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{
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{
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@ -880,7 +910,7 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
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.trigger = davinci_mcasp_trigger,
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.trigger = davinci_mcasp_trigger,
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.hw_params = davinci_mcasp_hw_params,
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.hw_params = davinci_mcasp_hw_params,
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.set_fmt = davinci_mcasp_set_dai_fmt,
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.set_fmt = davinci_mcasp_set_dai_fmt,
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.set_clkdiv = davinci_mcasp_set_clkdiv,
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};
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};
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#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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