ASoC: McASP: add support for clock dividers

Add support for the internal clock dividers of the McASP driver.

Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Daniel Mack 2012-10-04 15:08:39 +02:00 коммит произвёл Mark Brown
Родитель 393a53cbcf
Коммит 4ed8c9b737
1 изменённых файлов: 31 добавлений и 1 удалений

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@ -199,6 +199,7 @@
#define ACLKXE BIT(5) #define ACLKXE BIT(5)
#define TX_ASYNC BIT(6) #define TX_ASYNC BIT(6)
#define ACLKXPOL BIT(7) #define ACLKXPOL BIT(7)
#define ACLKXDIV_MASK 0x1f
/* /*
* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
@ -207,6 +208,7 @@
#define ACLKRE BIT(5) #define ACLKRE BIT(5)
#define RX_ASYNC BIT(6) #define RX_ASYNC BIT(6)
#define ACLKRPOL BIT(7) #define ACLKRPOL BIT(7)
#define ACLKRDIV_MASK 0x1f
/* /*
* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
@ -215,6 +217,7 @@
#define AHCLKXDIV(val) (val) #define AHCLKXDIV(val) (val)
#define AHCLKXPOL BIT(14) #define AHCLKXPOL BIT(14)
#define AHCLKXE BIT(15) #define AHCLKXE BIT(15)
#define AHCLKXDIV_MASK 0xfff
/* /*
* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
@ -223,6 +226,7 @@
#define AHCLKRDIV(val) (val) #define AHCLKRDIV(val) (val)
#define AHCLKRPOL BIT(14) #define AHCLKRPOL BIT(14)
#define AHCLKRE BIT(15) #define AHCLKRE BIT(15)
#define AHCLKRDIV_MASK 0xfff
/* /*
* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
@ -554,6 +558,32 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
return 0; return 0;
} }
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
switch (div_id) {
case 0: /* MCLK divider */
mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
break;
case 1: /* BCLK divider */
mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
ACLKXDIV(div - 1), ACLKXDIV_MASK);
mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
ACLKRDIV(div - 1), ACLKRDIV_MASK);
break;
default:
return -EINVAL;
}
return 0;
}
static int davinci_config_channel_size(struct davinci_audio_dev *dev, static int davinci_config_channel_size(struct davinci_audio_dev *dev,
int channel_size) int channel_size)
{ {
@ -880,7 +910,7 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
.trigger = davinci_mcasp_trigger, .trigger = davinci_mcasp_trigger,
.hw_params = davinci_mcasp_hw_params, .hw_params = davinci_mcasp_hw_params,
.set_fmt = davinci_mcasp_set_dai_fmt, .set_fmt = davinci_mcasp_set_dai_fmt,
.set_clkdiv = davinci_mcasp_set_clkdiv,
}; };
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \