From cea931c25104e6bddc42eb067f58193f355dbdd7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 10 Jan 2020 18:16:41 +0100 Subject: [PATCH 01/32] clocksource: davinci: only enable clockevents once tim34 is initialized The DM365 platform has a strange quirk (only present when using ancient u-boot - mainline u-boot v2013.01 and later works fine) where if we enable the second half of the timer in periodic mode before we do its initialization - the time won't start flowing and we can't boot. When using more recent u-boot, we can enable the timer, then reinitialize it and all works fine. To work around this issue only enable clockevents once tim34 is initialized i.e. move clockevents_config_and_register() below tim34 initialization. Signed-off-by: Bartosz Golaszewski Signed-off-by: Sekhar Nori --- drivers/clocksource/timer-davinci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c index 62745c962049..e421946a91c5 100644 --- a/drivers/clocksource/timer-davinci.c +++ b/drivers/clocksource/timer-davinci.c @@ -302,10 +302,6 @@ int __init davinci_timer_register(struct clk *clk, return rv; } - clockevents_config_and_register(&clockevent->dev, tick_rate, - DAVINCI_TIMER_MIN_DELTA, - DAVINCI_TIMER_MAX_DELTA); - davinci_clocksource.dev.rating = 300; davinci_clocksource.dev.read = davinci_clocksource_read; davinci_clocksource.dev.mask = @@ -323,6 +319,10 @@ int __init davinci_timer_register(struct clk *clk, davinci_clocksource_init_tim34(base); } + clockevents_config_and_register(&clockevent->dev, tick_rate, + DAVINCI_TIMER_MIN_DELTA, + DAVINCI_TIMER_MAX_DELTA); + rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate); if (rv) { pr_err("Unable to register clocksource"); From 20eb43540bd05fce8655747bec3af950eccc7eb0 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 10 Jan 2020 18:16:42 +0100 Subject: [PATCH 02/32] ARM: davinci: dm365: switch to using the clocksource driver We now have a proper clocksource driver for davinci. Switch the dm365 platform to using it. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/dm365.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 9fc5c73cc0be..c1e0d46996e4 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -35,7 +35,8 @@ #include #include #include -#include + +#include #include "asp.h" #include "davinci.h" @@ -660,10 +661,16 @@ static struct davinci_id dm365_ids[] = { }, }; -static struct davinci_timer_info dm365_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +/* + * Bottom half of timer0 is used for clockevent, top half is used for + * clocksource. + */ +static const struct davinci_timer_cfg dm365_timer_cfg = { + .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), + }, }; #define DM365_UART1_BASE (IO_PHYS + 0x106000) @@ -723,7 +730,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = { .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm365_pins, .pinmux_pins_num = ARRAY_SIZE(dm365_pins), - .timer_info = &dm365_timer_info, .emac_pdata = &dm365_emac_pdata, .sram_dma = 0x00010000, .sram_len = SZ_32K, @@ -771,6 +777,7 @@ void __init dm365_init_time(void) { void __iomem *pll1, *pll2, *psc; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ); @@ -789,7 +796,8 @@ void __init dm365_init_time(void) return; } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &dm365_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } void __init dm365_register_clocks(void) From 6b49d4fbcbc2ad98c234da2b344865508eed7bf4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 10 Jan 2020 18:16:43 +0100 Subject: [PATCH 03/32] ARM: davinci: remove legacy timer support All platforms have now been switched to the new clocksource driver. Remove the old code and various no longer needed bits and pieces. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Makefile | 3 +- arch/arm/mach-davinci/devices-da8xx.c | 1 - arch/arm/mach-davinci/devices.c | 19 - arch/arm/mach-davinci/include/mach/common.h | 17 - arch/arm/mach-davinci/include/mach/time.h | 33 -- arch/arm/mach-davinci/time.c | 400 -------------------- 6 files changed, 1 insertion(+), 472 deletions(-) delete mode 100644 arch/arm/mach-davinci/include/mach/time.h delete mode 100644 arch/arm/mach-davinci/time.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index a03d8443ef08..58838a9de651 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -7,8 +7,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include # Common objects -obj-y := time.o serial.o usb.o \ - common.o sram.o +obj-y := serial.o usb.o common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 2d69e704f7f6..feb206bdf6e1 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -21,7 +21,6 @@ #include #include #include -#include #include "asp.h" #include "cpuidle.h" diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 3e447d468845..d912d62a0eca 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "davinci.h" #include "irqs.h" @@ -303,21 +302,3 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata) davinci_gpio_device.dev.platform_data = pdata; return platform_device_register(&davinci_gpio_device); } - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -struct davinci_timer_instance davinci_timer_instance[2] = { - { - .base = DAVINCI_TIMER0_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12), - .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34), - }, - { - .base = DAVINCI_TIMER1_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12), - .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34), - }, -}; - diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 9526e5da0d33..139b83de011d 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -22,22 +22,6 @@ #define DAVINCI_INTC_START NR_IRQS #define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) -void davinci_timer_init(struct clk *clk); - -struct davinci_timer_instance { - u32 base; - u32 bottom_irq; - u32 top_irq; - unsigned long cmp_off; - unsigned int cmp_irq; -}; - -struct davinci_timer_info { - struct davinci_timer_instance *timers; - unsigned int clockevent_id; - unsigned int clocksource_id; -}; - struct davinci_gpio_controller; /* @@ -58,7 +42,6 @@ struct davinci_soc_info { u32 pinmux_base; const struct mux_config *pinmux_pins; unsigned long pinmux_pins_num; - struct davinci_timer_info *timer_info; int gpio_type; u32 gpio_base; unsigned gpio_num; diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h deleted file mode 100644 index ba913736990f..000000000000 --- a/arch/arm/mach-davinci/include/mach/time.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Local header file for DaVinci time code. - * - * Author: Kevin Hilman, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H -#define __ARCH_ARM_MACH_DAVINCI_TIME_H - -#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) - -enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS -}; - -#define IS_TIMER1(id) (id & 0x2) -#define IS_TIMER0(id) (!IS_TIMER1(id)) -#define IS_TIMER_TOP(id) ((id & 0x1)) -#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) - -#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0) - -extern struct davinci_timer_instance davinci_timer_instance[]; - -#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */ diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c deleted file mode 100644 index 740410a3bb6a..000000000000 --- a/arch/arm/mach-davinci/time.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * DaVinci timer subsystem - * - * Author: Kevin Hilman, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -static struct clock_event_device clockevent_davinci; -static unsigned int davinci_clock_tick_rate; - -/* - * This driver configures the 2 64-bit count-up timers as 4 independent - * 32-bit count-up timers used as follows: - */ - -enum { - TID_CLOCKEVENT, - TID_CLOCKSOURCE, -}; - -/* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 - -/* Offsets of the 8 compare registers */ -#define CMP12_0 0x60 -#define CMP12_1 0x64 -#define CMP12_2 0x68 -#define CMP12_3 0x6c -#define CMP12_4 0x70 -#define CMP12_5 0x74 -#define CMP12_6 0x78 -#define CMP12_7 0x7c - -/* Timer register bitfields */ -#define TCR_ENAMODE_DISABLE 0x0 -#define TCR_ENAMODE_ONESHOT 0x1 -#define TCR_ENAMODE_PERIODIC 0x2 -#define TCR_ENAMODE_MASK 0x3 - -#define TGCR_TIMMODE_SHIFT 2 -#define TGCR_TIMMODE_64BIT_GP 0x0 -#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 -#define TGCR_TIMMODE_64BIT_WDOG 0x2 -#define TGCR_TIMMODE_32BIT_CHAINED 0x3 - -#define TGCR_TIM12RS_SHIFT 0 -#define TGCR_TIM34RS_SHIFT 1 -#define TGCR_RESET 0x0 -#define TGCR_UNRESET 0x1 -#define TGCR_RESET_MASK 0x3 - -struct timer_s { - char *name; - unsigned int id; - unsigned long period; - unsigned long opts; - unsigned long flags; - void __iomem *base; - unsigned long tim_off; - unsigned long prd_off; - unsigned long enamode_shift; - struct irqaction irqaction; -}; -static struct timer_s timers[]; - -/* values for 'opts' field of struct timer_s */ -#define TIMER_OPTS_DISABLED 0x01 -#define TIMER_OPTS_ONESHOT 0x02 -#define TIMER_OPTS_PERIODIC 0x04 -#define TIMER_OPTS_STATE_MASK 0x07 - -#define TIMER_OPTS_USE_COMPARE 0x80000000 -#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE) - -static char *id_to_name[] = { - [T0_BOT] = "timer0_0", - [T0_TOP] = "timer0_1", - [T1_BOT] = "timer1_0", - [T1_TOP] = "timer1_1", -}; - -static int timer32_config(struct timer_s *t) -{ - u32 tcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (USING_COMPARE(t)) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id); - - /* - * Next interrupt should be the current time reg value plus - * the new period (using 32-bit unsigned addition/wrapping - * to 0 on overflow). This assumes that the clocksource - * is setup to count to 2^32-1 before wrapping around to 0. - */ - __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, - t->base + dtip[event_timer].cmp_off); - } else { - tcr = __raw_readl(t->base + TCR); - - /* disable timer */ - tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - __raw_writel(tcr, t->base + TCR); - - /* reset counter to zero, set new period */ - __raw_writel(0, t->base + t->tim_off); - __raw_writel(t->period, t->base + t->prd_off); - - /* Set enable mode */ - if (t->opts & TIMER_OPTS_ONESHOT) - tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; - else if (t->opts & TIMER_OPTS_PERIODIC) - tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; - - __raw_writel(tcr, t->base + TCR); - } - return 0; -} - -static inline u32 timer32_read(struct timer_s *t) -{ - return __raw_readl(t->base + t->tim_off); -} - -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_davinci; - - evt->event_handler(evt); - return IRQ_HANDLED; -} - -/* called when 32-bit counter wraps */ -static irqreturn_t freerun_interrupt(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static struct timer_s timers[] = { - [TID_CLOCKEVENT] = { - .name = "clockevent", - .opts = TIMER_OPTS_DISABLED, - .irqaction = { - .flags = IRQF_TIMER, - .handler = timer_interrupt, - } - }, - [TID_CLOCKSOURCE] = { - .name = "free-run counter", - .period = ~0, - .opts = TIMER_OPTS_PERIODIC, - .irqaction = { - .flags = IRQF_TIMER, - .handler = freerun_interrupt, - } - }, -}; - -static void __init timer_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct davinci_timer_instance *dtip = soc_info->timer_info->timers; - void __iomem *base[2]; - int i; - - /* Global init of each 64-bit timer as a whole */ - for(i=0; i<2; i++) { - u32 tgcr; - - base[i] = ioremap(dtip[i].base, SZ_4K); - if (WARN_ON(!base[i])) - continue; - - /* Disabled, Internal clock source */ - __raw_writel(0, base[i] + TCR); - - /* reset both timers, no pre-scaler for timer34 */ - tgcr = 0; - __raw_writel(tgcr, base[i] + TGCR); - - /* Set both timers to unchained 32-bit */ - tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - __raw_writel(tgcr, base[i] + TGCR); - - /* Unreset timers */ - tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | - (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base[i] + TGCR); - - /* Init both counters to zero */ - __raw_writel(0, base[i] + TIM12); - __raw_writel(0, base[i] + TIM34); - } - - /* Init of each timer as a 32-bit timer */ - for (i=0; i< ARRAY_SIZE(timers); i++) { - struct timer_s *t = &timers[i]; - int timer = ID_TO_TIMER(t->id); - u32 irq; - - t->base = base[timer]; - if (!t->base) - continue; - - if (IS_TIMER_BOT(t->id)) { - t->enamode_shift = 6; - t->tim_off = TIM12; - t->prd_off = PRD12; - irq = dtip[timer].bottom_irq; - } else { - t->enamode_shift = 22; - t->tim_off = TIM34; - t->prd_off = PRD34; - irq = dtip[timer].top_irq; - } - - /* Register interrupt */ - t->irqaction.name = t->name; - t->irqaction.dev_id = (void *)t; - - if (t->irqaction.handler != NULL) { - irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq; - setup_irq(irq, &t->irqaction); - } - } -} - -/* - * clocksource - */ -static u64 read_cycles(struct clocksource *cs) -{ - struct timer_s *t = &timers[TID_CLOCKSOURCE]; - - return (cycles_t)timer32_read(t); -} - -static struct clocksource clocksource_davinci = { - .rating = 300, - .read = read_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * Overwrite weak default sched_clock with something more precise - */ -static u64 notrace davinci_read_sched_clock(void) -{ - return timer32_read(&timers[TID_CLOCKSOURCE]); -} - -/* - * clockevent - */ -static int davinci_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->period = cycles; - timer32_config(t); - return 0; -} - -static int davinci_shutdown(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_DISABLED; - return 0; -} - -static int davinci_set_oneshot(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_ONESHOT; - return 0; -} - -static int davinci_set_periodic(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->period = davinci_clock_tick_rate / (HZ); - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_PERIODIC; - timer32_config(t); - return 0; -} - -static struct clock_event_device clockevent_davinci = { - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = davinci_set_next_event, - .set_state_shutdown = davinci_shutdown, - .set_state_periodic = davinci_set_periodic, - .set_state_oneshot = davinci_set_oneshot, -}; - -void __init davinci_timer_init(struct clk *timer_clk) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - unsigned int clockevent_id; - unsigned int clocksource_id; - int i; - - clockevent_id = soc_info->timer_info->clockevent_id; - clocksource_id = soc_info->timer_info->clocksource_id; - - timers[TID_CLOCKEVENT].id = clockevent_id; - timers[TID_CLOCKSOURCE].id = clocksource_id; - - /* - * If using same timer for both clock events & clocksource, - * a compare register must be used to generate an event interrupt. - * This is equivalent to a oneshot timer only (not periodic). - */ - if (clockevent_id == clocksource_id) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(clockevent_id); - - /* Only bottom timers can use compare regs */ - if (IS_TIMER_TOP(clockevent_id)) - pr_warn("%s: Invalid use of system timers. Results unpredictable.\n", - __func__); - else if ((dtip[event_timer].cmp_off == 0) - || (dtip[event_timer].cmp_irq == 0)) - pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n", - __func__); - else { - timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE; - clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT; - } - } - - BUG_ON(IS_ERR(timer_clk)); - clk_prepare_enable(timer_clk); - - /* init timer hw */ - timer_init(); - - davinci_clock_tick_rate = clk_get_rate(timer_clk); - - /* setup clocksource */ - clocksource_davinci.name = id_to_name[clocksource_id]; - if (clocksource_register_hz(&clocksource_davinci, - davinci_clock_tick_rate)) - pr_err("%s: can't register clocksource!\n", - clocksource_davinci.name); - - sched_clock_register(davinci_read_sched_clock, 32, - davinci_clock_tick_rate); - - /* setup clockevent */ - clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; - - clockevent_davinci.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_davinci, - davinci_clock_tick_rate, 1, 0xfffffffe); - - for (i=0; i< ARRAY_SIZE(timers); i++) - timer32_config(&timers[i]); -} From 9c76e8f65d2e73834fe1c83ed4394f3b4d485548 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 30 Aug 2019 13:22:52 +0300 Subject: [PATCH 04/32] ARM: davinci: dm365-evm: Add Fixed regulators needed for tlv320aic3101 The codec driver needs correct regulators in order to probe. Both VCC_3V3 and VCC_1V8 is always on fixed regulators on the board. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-dm365-evm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 150a36f333df..2328b15ac067 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include @@ -245,6 +247,19 @@ static struct davinci_i2c_platform_data i2c_pdata = { .bus_delay = 0 /* usec */, }; +/* Fixed regulator support */ +static struct regulator_consumer_supply fixed_supplies_3_3v[] = { + /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */ + REGULATOR_SUPPLY("AVDD", "1-0018"), + REGULATOR_SUPPLY("DRVDD", "1-0018"), + REGULATOR_SUPPLY("IOVDD", "1-0018"), +}; + +static struct regulator_consumer_supply fixed_supplies_1_8v[] = { + /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */ + REGULATOR_SUPPLY("DVDD", "1-0018"), +}; + static int dm365evm_keyscan_enable(struct device *dev) { return davinci_cfg_reg(DM365_KEYSCAN); @@ -800,6 +815,11 @@ static __init void dm365_evm_init(void) if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); + regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v, + ARRAY_SIZE(fixed_supplies_1_8v), 1800000); + regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v, + ARRAY_SIZE(fixed_supplies_3_3v), 3300000); + nvmem_add_cell_table(&davinci_nvmem_cell_table); nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1); From 5e06d19694a463a012c2589e29078196eb209448 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 30 Aug 2019 13:23:08 +0300 Subject: [PATCH 05/32] ARM: davinci: dm644x-evm: Add Fixed regulators needed for tlv320aic33 The codec driver needs correct regulators in order to probe. Both VCC_3.3V and VCC_1.8V is always on fixed regulators on the board. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-dm644x-evm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 9d87d4e440ea..8406c82e1da4 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include @@ -653,6 +655,19 @@ static struct i2c_board_info __initdata i2c_info[] = { }, }; +/* Fixed regulator support */ +static struct regulator_consumer_supply fixed_supplies_3_3v[] = { + /* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */ + REGULATOR_SUPPLY("AVDD", "1-001b"), + REGULATOR_SUPPLY("DRVDD", "1-001b"), +}; + +static struct regulator_consumer_supply fixed_supplies_1_8v[] = { + /* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */ + REGULATOR_SUPPLY("IOVDD", "1-001b"), + REGULATOR_SUPPLY("DVDD", "1-001b"), +}; + #define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12) #define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11) @@ -831,6 +846,11 @@ static __init void davinci_evm_init(void) dm644x_register_clocks(); + regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v, + ARRAY_SIZE(fixed_supplies_1_8v), 1800000); + regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v, + ARRAY_SIZE(fixed_supplies_3_3v), 3300000); + dm644x_init_devices(); ret = dm644x_gpio_register(); From cfcbc2dbb70826b91aa45ae37168b2db2aac1803 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:10 -0800 Subject: [PATCH 06/32] ARM: dts: Add missing omap4 secure clocks The secure clocks on omap4 are similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table 3-1346 L4PER_CM2 Registers Mapping Summary". The secure clocks are part of the l4_per clock manager. As the l4_per clock manager has now two clock domains as children, let's also update the l4_per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Cc: devicetree@vger.kernel.org Cc: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 11 ++++++++--- drivers/clk/ti/clk-44xx.c | 13 +++++++++++++ include/dt-bindings/clock/omap4.h | 11 +++++++++++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index e9d9c8460682..532868591107 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -1279,13 +1279,18 @@ #size-cells = <1>; ranges = <0 0x1400 0x200>; - l4_per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; + l4_per_clkctrl: clock@20 { + compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; - }; + l4_secure_clkctrl: clock@1a0 { + compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; + reg = <0x1a0 0x3c>; + #clock-cells = <2>; + }; + }; }; &prm { diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 2b4dab632318..312a20f8ec0e 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons { 0 }, }; +static const struct +omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = { + { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { 0 }, +}; + static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = { { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, { 0 }, @@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = { { 0x4a009220, omap4_l3_gfx_clkctrl_regs }, { 0x4a009320, omap4_l3_init_clkctrl_regs }, { 0x4a009420, omap4_l4_per_clkctrl_regs }, + { 0x4a0095a0, omap4_l4_secure_clkctrl_regs }, { 0x4a307820, omap4_l4_wkup_clkctrl_regs }, { 0x4a307a20, omap4_emu_sys_clkctrl_regs }, { 0 }, diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h index 5167b2d93ac3..88d73be84b94 100644 --- a/include/dt-bindings/clock/omap4.h +++ b/include/dt-bindings/clock/omap4.h @@ -124,6 +124,17 @@ #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) +/* l4_secure clocks */ +#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) + /* l4_wkup clocks */ #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) From 723a567f43b8ffa8089009bc8a260cc6f963661e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:10 -0800 Subject: [PATCH 07/32] ARM: dts: Add missing omap5 secure clocks The secure clocks on omap5 are similar to what we already have for dra7 with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in "Table 3-1044. CORE_CM_CORE Registers Mapping Summary". The secure clocks are part of the l4per clock manager. As the l4per clock manager has now two clock domains as children, let's also update the l4per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Compared to omap4, omap5 has more clocks working in hardare autogating mode. Cc: devicetree@vger.kernel.org Cc: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 10 ++++++++-- drivers/clk/ti/clk-54xx.c | 13 +++++++++++++ include/dt-bindings/clock/omap5.h | 11 +++++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4791834dacb2..42f2c447727d 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -1125,11 +1125,17 @@ #size-cells = <1>; ranges = <0 0x1000 0x200>; - l4per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; + l4per_clkctrl: clock@20 { + compatible = "ti,clkctrl-l4per", "ti,clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; + + l4sec_clkctrl: clock@1a0 { + compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; + reg = <0x1a0 0x3c>; + #clock-cells = <2>; + }; }; dss_cm: dss_cm@1400 { diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 14d98a890c02..92bf2dda95b9 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -301,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst { 0 }, }; +static const struct +omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = { + { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { 0 }, +}; + static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = { { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, @@ -523,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, { 0x4a008e20, omap5_l3instr_clkctrl_regs }, { 0x4a009020, omap5_l4per_clkctrl_regs }, + { 0x4a0091a0, omap5_l4_secure_clkctrl_regs }, { 0x4a009220, omap5_iva_clkctrl_regs }, { 0x4a009420, omap5_dss_clkctrl_regs }, { 0x4a009520, omap5_gpu_clkctrl_regs }, diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index 2b4fd9a96b91..41775272fd27 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -87,6 +87,17 @@ #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +/* l4_secure clocks */ +#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) + /* iva clocks */ #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) From fbb8bb8370f6fdaaaccf85201f4ee2a665aae42d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:11 -0800 Subject: [PATCH 08/32] ARM: dts: Configure omap4 rng to probe with ti-sysc Add RNG interconnect data for omap4 similar to what dra7 has. The clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0, which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0). Note that we need to also add the related l4_secure clock entries. I've only added RNG, the others can be added as they get tested. They are probably very similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs[]. With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure devices and clk_get() will fail. Additionally we disable the RNG target module on droid4 to avoid introducing new boot time warnings. Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren --- .../boot/dts/motorola-mapphone-common.dtsi | 5 +++++ arch/arm/boot/dts/omap4-l4.dtsi | 20 ++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index da6b107da84a..71e7ea903eb5 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -650,6 +650,11 @@ }; }; +/* RNG is used by secure mode and not accessible */ +&rng_target { + status = "disabled"; +}; + /* Configure pwm clock source for timers 8 & 9 */ &timer8 { assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 83f803be8ee2..e8fa3f389f25 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -2002,12 +2002,26 @@ }; }; - target-module@90000 { /* 0x48090000, ap 57 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; }; target-module@96000 { /* 0x48096000, ap 37 26.0 */ From 30c2d7ca3fbcee7920979097b2d9bd5b0114ff68 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:11 -0800 Subject: [PATCH 09/32] ARM: dts: Configure omap5 rng to probe with ti-sysc This is similar to dra7 and omap4 with different clock naming and module address. Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 25aacf1ba708..b931090ce9a6 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1769,12 +1769,26 @@ }; }; - target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; }; target-module@98000 { /* 0x48098000, ap 47 08.0 */ From 18c48e6d5bb21558ea7f9bcc8e263b83fbad127a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:12 -0800 Subject: [PATCH 10/32] ARM: dts: Configure interconnect target module for omap4 sham We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2de8a6b53de9..e3c0732a1a3f 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -293,13 +293,33 @@ dma-names = "tx", "rx"; }; - sham: sham@4b100000 { - compatible = "ti,omap4-sham"; + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; ti,hwmods = "sham"; - reg = <0x4b100000 0x300>; - interrupts = ; - dmas = <&sdma 119>; - dma-names = "rx"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; }; abb_mpu: regulator-abb-mpu { From 316a418e28b6a4c72b991eebdd191c44ad5c2215 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:12 -0800 Subject: [PATCH 11/32] ARM: dts: Configure interconnect target module for omap4 aes We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 66 +++++++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e3c0732a1a3f..40212fa6a8cf 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -266,22 +266,64 @@ hw-caps-temp-alert; }; - aes1: aes@4b501000 { - compatible = "ti,omap4-aes"; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes1"; - reg = <0x4b501000 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; }; - aes2: aes@4b701000 { - compatible = "ti,omap4-aes"; + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes2"; - reg = <0x4b701000 0xa0>; - interrupts = ; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; }; des: des@480a5000 { From 23673f17358ac2bb4d3b33dad3f5645b54937344 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:13 -0800 Subject: [PATCH 12/32] ARM: dts: Configure interconnect target module for omap4 des We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 9 --------- 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index e8fa3f389f25..aa5a0705b460 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -2185,6 +2185,36 @@ <0x00001000 0x000a5000 0x00001000>; }; + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "des"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ compatible = "ti,sysc"; status = "disabled"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 40212fa6a8cf..277d3455293f 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -326,15 +326,6 @@ }; }; - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - sham_target: target-module@4b100000 { compatible = "ti,sysc-omap3-sham", "ti,sysc"; ti,hwmods = "sham"; From 814b253877345d01d78ea4786ad246c16e537378 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:13 -0800 Subject: [PATCH 13/32] ARM: OMAP2+: Drop legacy platform data for omap4 aes We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 2 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 62 ---------------------- 2 files changed, 64 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 277d3455293f..1c528acaee4b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -268,7 +268,6 @@ aes1_target: target-module@4b501000 { compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "aes1"; reg = <0x4b501080 0x4>, <0x4b501084 0x4>, <0x4b501088 0x4>; @@ -298,7 +297,6 @@ aes2_target: target-module@4b701000 { compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "aes2"; reg = <0x4b701080 0x4>, <0x4b701084 0x4>, <0x4b701088 0x4>; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 292f544bd62d..48ea81759056 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -884,66 +884,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { }, }; -/* - Crypto modules AES0/1 belong to: - PD_L4_PER power domain - CD_L4_SEC clock domain - On the L3, the AES modules are mapped to - L3_CLK2: Peripherals and multimedia sub clock domain -*/ -static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = { - .rev_offs = 0x80, - .sysc_offs = 0x84, - .syss_offs = 0x88, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_aes_hwmod_class = { - .name = "aes", - .sysc = &omap44xx_aes_sysc, -}; - -static struct omap_hwmod omap44xx_aes1_hwmod = { - .name = "aes1", - .class = &omap44xx_aes_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_aes1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_aes2_hwmod = { - .name = "aes2", - .class = &omap44xx_aes_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_aes2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; /* * 'des' class for DES3DES module @@ -3045,8 +2985,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__usb_tll_hs, &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, - &omap44xx_l3_main_2__aes1, - &omap44xx_l3_main_2__aes2, &omap44xx_l3_main_2__des, &omap44xx_l3_main_2__sha0, NULL, From bea5e904728e797fce2fb21e119f3831aa640d07 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:13 -0800 Subject: [PATCH 14/32] ARM: OMAP2+: Drop legacy platform data for omap4 sham We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 35 ---------------------- 2 files changed, 36 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1c528acaee4b..79cfa42e0054 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -326,7 +326,6 @@ sham_target: target-module@4b100000 { compatible = "ti,sysc-omap3-sham", "ti,sysc"; - ti,hwmods = "sham"; reg = <0x4b100100 0x4>, <0x4b100110 0x4>, <0x4b100114 0x4>; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 48ea81759056..0a05e340cdb0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -777,32 +777,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), }; -/* sha0 HIB2 (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = { - .rev_offs = 0x100, - .sysc_offs = 0x110, - .syss_offs = 0x114, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_sha0_hwmod_class = { - .name = "sham", - .sysc = &omap44xx_sha0_sysc, -}; - -static struct omap_hwmod omap44xx_sha0_hwmod = { - .name = "sham", - .class = &omap44xx_sha0_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; /* * 'elm' class @@ -2545,14 +2519,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; -/* l3_main_2 -> sham */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_sha0_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_per -> elm */ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { .master = &omap44xx_l4_per_hwmod, @@ -2986,7 +2952,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, &omap44xx_l3_main_2__des, - &omap44xx_l3_main_2__sha0, NULL, }; From ddf664da3b9c6d5c31e0d0c6e5aeb3e65250fdff Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:14 -0800 Subject: [PATCH 15/32] ARM: OMAP2+: Drop legacy platform data for omap4 des We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 1 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 38 ---------------------- 2 files changed, 39 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index aa5a0705b460..2b6eb8a4d968 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -2187,7 +2187,6 @@ des_target: target-module@a5000 { /* 0x480a5000 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "des"; reg = <0xa5030 0x4>, <0xa5034 0x4>, <0xa5038 0x4>; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0a05e340cdb0..f85ce74a1f4d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -858,43 +858,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { }, }; - -/* - * 'des' class for DES3DES module - */ -static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = { - .rev_offs = 0x30, - .sysc_offs = 0x34, - .syss_offs = 0x38, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_des_hwmod_class = { - .name = "des", - .sysc = &omap44xx_des_sysc, -}; - -static struct omap_hwmod omap44xx_des_hwmod = { - .name = "des", - .class = &omap44xx_des_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_des_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'fdif' class * face detection hw accelerator module @@ -2951,7 +2914,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__usb_tll_hs, &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, - &omap44xx_l3_main_2__des, NULL, }; From 215d103f36626da36c424aa7309ae1b5e7e38d14 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:50 -0600 Subject: [PATCH 16/32] ARM: dts: dra7: add cam clkctrl node Add clkctrl nodes for CAM domain. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "cam-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Signed-off-by: Benoit Parrot Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index ccf0fd477cf9..8eb31b83ed43 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1720,6 +1720,20 @@ }; }; + cam_cm: cam-cm@1000 { + compatible = "ti,omap4-cm"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x100>; + + cam_clkctrl: cam-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x2c>; + #clock-cells = <2>; + }; + }; + dss_cm: dss-cm@1100 { compatible = "ti,omap4-cm"; reg = <0x1100 0x100>; From 2baee0c5b359a4ce76f56b06c6cc4d7d642537a9 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:51 -0600 Subject: [PATCH 17/32] ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only Both CAL and VIP rely on this clock domain. But CAL DPHY require LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK is sourcing the input clock to the DPHY then actual frame capture cannot start as the phy are inactive. So we either have to also enabled VIP1 even if we don't intend on using it or we need to set the CAM domain to use SWSUP only. This patch implements the latter. Signed-off-by: Benoit Parrot Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 3068802824b7..27835c4d1aa9 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = { .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, .wkdep_srcs = cam_wkup_sleep_deps, .sleepdep_srcs = cam_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4per_7xx_clkdm = { From b31617258977ff1e63c8c3582fb27207f8ec292d Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:52 -0600 Subject: [PATCH 18/32] ARM: dts: dra7-l4: Add ti-sysc node for CAM Add CAM nodes as a child of l4 interconnect in order for it to probe using ti-sysc. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 43 +++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 7e7aa101d8a4..87f3b10d3c89 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -4166,27 +4166,58 @@ }; target-module@170000 { /* 0x48970000, ap 21 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x170010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x170000 0x10000>; + status = "disabled"; }; target-module@190000 { /* 0x48990000, ap 23 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x190010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x190000 0x10000>; + status = "disabled"; }; target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1b0000 0x10000>; + status = "disabled"; }; target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ From 86a7e226dd73f8676f2bee6dccf5a705f649521a Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:53 -0600 Subject: [PATCH 19/32] ARM: dts: DRA72: Add CAL dtsi node This patch adds the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA72 family of devices. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72x.dtsi | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f5762709c853..82b57a35abc0 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -17,6 +17,48 @@ }; }; +&l4_per2 { + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + cal: cal@0 { + compatible = "ti,dra72-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + ti,camerrx-control = <&scm_conf 0xE94>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>, From 414dc3d33b912fb1a98b0d2df05e16e359705fd3 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:54 -0600 Subject: [PATCH 20/32] arm: dts: dra72-evm-common: Add entries for the CSI2 cameras Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72-evm-common.dtsi | 31 +++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 9eabfd1502da..01558a86af82 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -187,6 +187,12 @@ gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + clk_ov5640_fixed: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &dra7_pmx_core { @@ -269,6 +275,23 @@ line-name = "vin6_sel_s0"; }; }; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; &uart1 { @@ -580,3 +603,11 @@ &pcie1_rc { status = "okay"; }; + +&csi2_0 { + csi2_phy0: endpoint { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; From 807276375ff44bdd5f94d26021ae630b5ed64bfc Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:55 -0600 Subject: [PATCH 21/32] arm: dtsi: dra76x: Add CAL dtsi node Add the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA76 family of devices. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76x.dtsi | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index cdcba3f561c4..2f7539afef2b 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -41,6 +41,48 @@ }; +&l4_per3 { + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + cal: cal@0 { + compatible = "ti,dra76-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + ti,camerrx-control = <&scm_conf 0x6dc>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + /* MCAN interrupts are hard-wired to irqs 67, 68 */ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>; From 3bd7b487a6dd3e43475bb473ecb8b9c5203a0de1 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:05:56 -0600 Subject: [PATCH 22/32] arm: dts: dra76-evm: Add CAL and OV5640 nodes Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76-evm.dts | 35 +++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 1fb6f13fb5e2..a17d4875bb2e 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -116,6 +116,12 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + clk_ov5640_fixed: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &i2c1 { @@ -317,6 +323,27 @@ }; }; +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + &cpu0 { vdd-supply = <&buck10_reg>; }; @@ -447,3 +474,11 @@ max-bitrate = <5000000>; }; }; + +&csi2_0 { + csi2_phy0: endpoint { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; From 01053dadb79d63b65f7b353e68b4b6ccf4effedb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 11 Dec 2019 08:07:18 -0600 Subject: [PATCH 23/32] ARM: dts: am43xx: add support for clkout1 clock clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec. commit 664ae1ab2536 ("ARM: dts: am43xx: add clkctrl nodes") effectively reverted this commit 8010f13a40d3 ("ARM: dts: am43xx: add support for clkout1 clock") which is needed for the ov2659 camera sensor clock definition hence it is being re-applied here. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "clkout1-*ck" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Fixes: 664ae1ab2536 ("ARM: dts: am43xx: add clkctrl nodes") Signed-off-by: Tero Kristo Tested-by: Benoit Parrot Acked-by: Tony Lindgren Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43xx-clocks.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 091356f2a8c1..c726cd8dbdf1 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -704,6 +704,60 @@ ti,bit-shift = <8>; reg = <0x2a48>; }; + + clkout1_osc_div_ck: clkout1-osc-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <20>; + ti,max-div = <4>; + reg = <0x4100>; + }; + + clkout1_src2_mux_ck: clkout1-src2-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>; + reg = <0x4100>; + }; + + clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4100>; + }; + + clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4100>; + }; + + clkout1_mux_ck: clkout1-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, + <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; + ti,bit-shift = <16>; + reg = <0x4100>; + }; + + clkout1_ck: clkout1-ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout1_mux_ck>; + ti,bit-shift = <23>; + reg = <0x4100>; + }; }; &prcm { From f8404f159515eae8495ec042ab964660fcc165ce Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:07:19 -0600 Subject: [PATCH 24/32] ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries Add VPFE device nodes entries. Add OmniVision OV2659 sensor device nodes and linkage. The sensor clock (xvclk) is sourced from clkout1. Add clock entries to properly select clkout1 and set its parent clock to sys_clkin_ck. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-sk-evm.dts | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 74eaa6a3b258..25222497f828 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -272,6 +272,12 @@ >; }; + clkout1_pin: pinmux_clkout1_pin { + pinctrl-single,pins = < + 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ + >; + }; + cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -593,6 +599,25 @@ pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&clkout1_pin>; + + clocks = <&clkout1_mux_ck>; + clock-names = "xvclk"; + assigned-clocks = <&clkout1_mux_ck>; + assigned-clock-parents = <&clkout1_osc_div_ck>; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + edt-ft5306@38 { status = "okay"; compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; @@ -877,7 +902,7 @@ /* Camera port */ port { vpfe0_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; From d916ab415b5f4583e79ecd6ecc17b0bd414abcc3 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:07:20 -0600 Subject: [PATCH 25/32] ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries Add VPFE device nodes entries. Add OmniVision OV2659 sensor device nodes and linkage. Since Rev1.2a on this board the sensor source clock (xvclk) has a dedicated 12Mhz oscillator instead of using clkout1. Add 'audio_mstrclk' fixed clock object to represent it. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 95314121d111..b0df37014888 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -145,6 +145,12 @@ system-clock-frequency = <12000000>; }; }; + + audio_mstrclk: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &am43xx_pinmux { @@ -696,6 +702,21 @@ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&audio_mstrclk>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; }; &i2c2 { @@ -962,7 +983,7 @@ port { vpfe1_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; From 79312524dbf1c3b24226e1804235c2578422c86d Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:08:09 -0600 Subject: [PATCH 26/32] ARM: dts: dra7: add vpe clkctrl node Add clkctrl nodes for VPE module. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "vpe-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Signed-off-by: Benoit Parrot Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8eb31b83ed43..55cef4cac5f1 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1591,10 +1591,10 @@ rtc_cm: rtc-cm@700 { compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; + reg = <0x700 0x60>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x700 0x100>; + ranges = <0 0x700 0x60>; rtc_clkctrl: rtc-clkctrl@20 { compatible = "ti,clkctrl"; @@ -1603,6 +1603,20 @@ }; }; + vpe_cm: vpe-cm@760 { + compatible = "ti,omap4-cm"; + reg = <0x760 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x760 0xc>; + + vpe_clkctrl: vpe-clkctrl@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0xc>; + #clock-cells = <2>; + }; + }; + }; &cm_core { From 1a2095160594f52ce8fecca634038f1deeb3577c Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Wed, 11 Dec 2019 08:08:10 -0600 Subject: [PATCH 27/32] ARM: dts: dra7: Add ti-sysc node for VPE Add VPE node as a child of l4 interconnect in order for it to probe using ti-sysc. Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 87f3b10d3c89..7f76411d2876 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -4220,12 +4220,34 @@ status = "disabled"; }; - target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; + target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1d0010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1d0000 0x10000>; + + vpe: vpe@0 { + compatible = "ti,dra7-vpe"; + reg = <0x0000 0x120>, + <0x0700 0x80>, + <0x5700 0x18>, + <0xd000 0x400>; + reg-names = "vpe_top", + "sc", + "csc", + "vpdma"; + interrupts = ; + }; }; }; }; From c3fb99f46efdd34ea84c1968065aaa15164d4500 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Aug 2019 06:14:08 -0700 Subject: [PATCH 28/32] ARM: dts: Configure rstctrl reset for am335x SGX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following can be tested via sysfs with the following to ensure the SGX module gets enabled and disabled properly: # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5600fe00 # revision register 0x5600fe00 = 0x40000000 # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5000fe00 Bus error Note that this patch depends on the PRM rstctrl driver that has been recently posted. If the child device driver(s) need to prevent rstctrl reset on PM runtime suspend, the drivers need to increase the usecount for the shared rstctrl reset that can be mapped also for the child device(s) or accessed via dev->parent. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 646f11430dad..c427ce8c2539 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -457,6 +457,31 @@ <&edma 5 0>; dma-names = "tx", "rx"; }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_gfx 0>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x1000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; }; }; From 45e118b7805e618db39a2b1b85bd50d8c8614643 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 1 Nov 2019 09:31:23 -0700 Subject: [PATCH 29/32] ARM: dts: Configure sgx for dra7 I've tested that the interconnect target module enables and idles just fine when probed with ti-sysc with PM runtime control via sys: # echo on > $(find /sys -name control | grep \/5600) # rwmem 0x5600fe00 # OCP Revision 0x5600fe00 = 0x40000000 # echo auto > $(find /sys -name control | grep \/5600) Cc: "H. Nikolaus Schaller" Cc: Robert Nelson Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 73e5011f531a..ead1000ddec5 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -597,6 +597,24 @@ status = "disabled"; }; + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + }; + crossbar_mpu: crossbar@4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; From a5ebccc822d8f84cd899e3e64f770f2bd4d7951b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 8 Nov 2019 13:31:25 -0800 Subject: [PATCH 30/32] ARM: dts: Configure interconnect target module for am437x sgx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This seems to be similar to what we have for am335x. The following can be tested via sysfs with the to ensure the SGX module gets enabled and disabled properly: # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5600fe00 # revision register 0x5600fe00 = 0x40000000 # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5000fe00 Bus error Note that this patch depends on the PRM rstctrl driver that has been recently posted. If the child device driver(s) need to prevent rstctrl reset on PM runtime suspend, the drivers need to increase the usecount for the shared rstctrl reset that can be mapped also for the child device(s) or accessed via dev->parent. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ca0aa3f26c0a..e2ee7c1bc7e5 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -369,6 +369,26 @@ pool; }; }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_gfx 0>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x1000000>; + }; }; }; From 36f808f2f1e9edb6fb129002a5ae71551b925225 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 19 Jan 2020 11:45:01 -0800 Subject: [PATCH 31/32] ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt We added coulomb counter calibration support With commit 0cb90f071f73 ("power: supply: cpcap-battery: Add basic coulomb counter calibrate support"), but we also need to configure the related interrupt. Without the interrupt calibration happens based on a timeout after two seconds, with the interrupt the calibration just gets done a bit faster. Cc: Merlijn Wajer Cc: Pavel Machek Acked-by: Pavel Machek Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi index 936ad010c83a..e39eee628afd 100644 --- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi @@ -27,11 +27,12 @@ compatible = "motorola,cpcap-battery"; interrupts-extended = < &cpcap 6 0 &cpcap 5 0 &cpcap 3 0 - &cpcap 20 0 &cpcap 54 0 + &cpcap 20 0 &cpcap 54 0 &cpcap 57 0 >; interrupt-names = "eol", "lowbph", "lowbpl", - "chrgcurr1", "battdetb"; + "chrgcurr1", "battdetb", + "cccal"; io-channels = <&cpcap_adc 0 &cpcap_adc 1 &cpcap_adc 5 &cpcap_adc 6>; io-channel-names = "battdetb", "battp", From 2256e6f68c9e02524182640ba9584d978d490145 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 19 Jan 2020 11:56:59 -0800 Subject: [PATCH 32/32] ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem With "[PATCHv3] w1: omap-hdq: Simplify driver with PM runtime autosuspend" we can read the droid4 battery information over 1-wire with this patch with something like: # modprobe omap_hdq # hd /sys/bus/w1/devices/89-*/89-*/nvmem ... Unfortunately the format of the battery data seems to be Motorola specific and is currently unusable for battery charger unless somebody figures out what it means. Note that currently keeping omap_hdq module loaded will cause extra power consumption as it seems to scan devices periodically. Cc: Merlijn Wajer Cc: Pavel Machek Acked-by: Pavel Machek Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index da6b107da84a..9f3e89bcb496 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -249,6 +249,13 @@ }; }; +/* Battery NVRAM on 1-wire handled by w1_ds250x driver */ +&hdqw1w { + pinctrl-0 = <&hdq_pins>; + pinctrl-names = "default"; + ti,mode = "1w"; +}; + &i2c1 { tmp105@48 { compatible = "ti,tmp105"; @@ -440,6 +447,13 @@ >; }; + hdq_pins: pinmux_hdq_pins { + pinctrl-single,pins = < + /* 0x4a100120 hdq_sio.hdq_sio aa27 */ + OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) + >; + }; + /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ dss_hdmi_pins: pinmux_dss_hdmi_pins { pinctrl-single,pins = <