Merge branch 'pci/host-rcar' into next
* pci/host-rcar: PCI: Add R-Car Gen2 internal PCI support
This commit is contained in:
Bjorn Helgaas
Коммит
4efc52a9c2
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@ -25,4 +25,12 @@ config PCI_TEGRA
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bool "NVIDIA Tegra PCIe controller"
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depends on ARCH_TEGRA
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config PCI_RCAR_GEN2
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bool "Renesas R-Car Gen2 Internal PCI controller"
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depends on ARM && (ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST)
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help
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Say Y here if you want internal PCI support on R-Car Gen2 SoC.
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There are 3 internal PCI controllers available with a single
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built-in EHCI/OHCI host controller present on each one.
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endmenu
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@ -3,3 +3,4 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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@ -0,0 +1,333 @@
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/*
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* pci-rcar-gen2: internal PCI bus support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* AHB-PCI Bridge PCI communication registers */
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#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
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#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
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#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
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#define RCAR_PCIAHB_PREFETCH0 0x0
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#define RCAR_PCIAHB_PREFETCH4 0x1
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#define RCAR_PCIAHB_PREFETCH8 0x2
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#define RCAR_PCIAHB_PREFETCH16 0x3
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#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
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#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
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#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
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#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
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#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
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#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
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#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
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#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
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#define RCAR_PCI_INT_A (1 << 16)
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#define RCAR_PCI_INT_B (1 << 17)
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#define RCAR_PCI_INT_PME (1 << 19)
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#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
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#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
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#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
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#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
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#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
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#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
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#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
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RCAR_AHB_BUS_MMODE_BYTE_BURST | \
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RCAR_AHB_BUS_MMODE_WR_INCR | \
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RCAR_AHB_BUS_MMODE_HBUS_REQ | \
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RCAR_AHB_BUS_SMODE_READYCTR)
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#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
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#define RCAR_USBCTR_USBH_RST (1 << 0)
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#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
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#define RCAR_USBCTR_PLL_RST (1 << 2)
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#define RCAR_USBCTR_DIRPD (1 << 8)
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#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
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#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
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#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
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#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
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#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
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#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
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#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
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/* Number of internal PCI controllers */
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#define RCAR_PCI_NR_CONTROLLERS 3
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struct rcar_pci_priv {
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void __iomem *reg;
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struct resource io_res;
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struct resource mem_res;
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struct resource *cfg_res;
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int irq;
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};
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/* PCI configuration space operations */
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static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct rcar_pci_priv *priv = sys->private_data;
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int slot, val;
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if (sys->busnr != bus->number || PCI_FUNC(devfn))
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return NULL;
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/* Only one EHCI/OHCI device built-in */
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slot = PCI_SLOT(devfn);
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if (slot > 2)
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return NULL;
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val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
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RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
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iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
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return priv->reg + (slot >> 1) * 0x100 + where;
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}
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static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
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if (!reg)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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*val = ioread8(reg);
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break;
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case 2:
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*val = ioread16(reg);
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break;
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default:
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*val = ioread32(reg);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
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if (!reg)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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iowrite8(val, reg);
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break;
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case 2:
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iowrite16(val, reg);
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break;
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default:
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iowrite32(val, reg);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/* PCI interrupt mapping */
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static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pci_sys_data *sys = dev->bus->sysdata;
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struct rcar_pci_priv *priv = sys->private_data;
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return priv->irq;
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}
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/* PCI host controller setup */
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static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct rcar_pci_priv *priv = sys->private_data;
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void __iomem *reg = priv->reg;
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u32 val;
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val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
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pr_info("PCI: bus%u revision %x\n", sys->busnr, val);
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/* Disable Direct Power Down State and assert reset */
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val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
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val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
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iowrite32(val, reg + RCAR_USBCTR_REG);
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udelay(4);
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/* De-assert reset and set PCIAHB window1 size to 1GB */
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val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
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RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
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iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
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/* Configure AHB master and slave modes */
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iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
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/* Configure PCI arbiter */
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val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
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val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
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RCAR_PCI_ARBITER_PCIBP_MODE;
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iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
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/* PCI-AHB mapping: 0x40000000-0x80000000 */
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iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
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reg + RCAR_PCIAHB_WIN1_CTR_REG);
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/* AHB-PCI mapping: OHCI/EHCI registers */
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val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
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iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
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/* Enable AHB-PCI bridge PCI configuration access */
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iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
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reg + RCAR_AHBPCI_WIN1_CTR_REG);
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/* Set PCI-AHB Window1 address */
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iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
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reg + PCI_BASE_ADDRESS_1);
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/* Set AHB-PCI bridge PCI communication area address */
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val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
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iowrite32(val, reg + PCI_BASE_ADDRESS_0);
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val = ioread32(reg + PCI_COMMAND);
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val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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iowrite32(val, reg + PCI_COMMAND);
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/* Enable PCI interrupts */
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iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
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reg + RCAR_PCI_INT_ENABLE_REG);
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/* Add PCI resources */
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pci_add_resource(&sys->resources, &priv->io_res);
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pci_add_resource(&sys->resources, &priv->mem_res);
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return 1;
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}
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static struct pci_ops rcar_pci_ops = {
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.read = rcar_pci_read_config,
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.write = rcar_pci_write_config,
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};
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static struct hw_pci rcar_hw_pci __initdata = {
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.map_irq = rcar_pci_map_irq,
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.ops = &rcar_pci_ops,
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.setup = rcar_pci_setup,
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};
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static int rcar_pci_count __initdata;
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static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
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{
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void **private_data;
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int count;
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if (rcar_hw_pci.nr_controllers < rcar_pci_count)
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goto add_priv;
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/* (Re)allocate private data pointer array if needed */
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count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
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private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
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if (!private_data)
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return -ENOMEM;
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rcar_pci_count = count;
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if (rcar_hw_pci.private_data) {
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memcpy(private_data, rcar_hw_pci.private_data,
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rcar_hw_pci.nr_controllers * sizeof(void *));
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kfree(rcar_hw_pci.private_data);
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}
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rcar_hw_pci.private_data = private_data;
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add_priv:
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/* Add private data pointer to the array */
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rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
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return 0;
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}
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static int __init rcar_pci_probe(struct platform_device *pdev)
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{
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struct resource *cfg_res, *mem_res;
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struct rcar_pci_priv *priv;
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void __iomem *reg;
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cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, cfg_res);
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if (!reg)
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return -ENODEV;
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mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!mem_res || !mem_res->start)
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return -ENODEV;
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priv = devm_kzalloc(&pdev->dev,
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sizeof(struct rcar_pci_priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->mem_res = *mem_res;
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/*
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* The controller does not support/use port I/O,
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* so setup a dummy port I/O region here.
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*/
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priv->io_res.start = priv->mem_res.start;
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priv->io_res.end = priv->mem_res.end;
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priv->io_res.flags = IORESOURCE_IO;
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priv->cfg_res = cfg_res;
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priv->irq = platform_get_irq(pdev, 0);
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priv->reg = reg;
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return rcar_pci_add_controller(priv);
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}
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static struct platform_driver rcar_pci_driver = {
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.driver = {
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.name = "pci-rcar-gen2",
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},
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};
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static int __init rcar_pci_init(void)
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{
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int retval;
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retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
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if (!retval)
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pci_common_init(&rcar_hw_pci);
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/* Private data pointer array is not needed any more */
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kfree(rcar_hw_pci.private_data);
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rcar_hw_pci.private_data = NULL;
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return retval;
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}
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subsys_initcall(rcar_pci_init);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
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MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");
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