cxl/pci: Defer mailbox status checks to command timeouts
Device status can change without warning at any point in time. This effectively means that no amount of status checking before a command is submitted can guarantee that the device is not in an error condition when the command is later submitted. The clearest signal that a device is not able to process commands is if it fails to process commands. With the above understanding in hand, update cxl_pci_setup_mailbox() to validate the readiness of the mailbox once at the beginning of time, and then use timeouts and busy sequencing errors as the only occasions to report status. Just as before, unless and until the driver gains a reset recovery path, doorbell clearing failures by the device are fatal to mailbox operations. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164298413480.3018233.9643395389297971819.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
Родитель
229e8828c2
Коммит
4f195ee73a
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@ -73,14 +73,16 @@ static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds)
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return 0;
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}
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static void cxl_pci_mbox_timeout(struct cxl_dev_state *cxlds,
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struct cxl_mbox_cmd *mbox_cmd)
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{
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struct device *dev = cxlds->dev;
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#define cxl_err(dev, status, msg) \
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dev_err_ratelimited(dev, msg ", device state %s%s\n", \
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status & CXLMDEV_DEV_FATAL ? " fatal" : "", \
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status & CXLMDEV_FW_HALT ? " firmware-halt" : "")
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dev_dbg(dev, "Mailbox command (opcode: %#x size: %zub) timed out\n",
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mbox_cmd->opcode, mbox_cmd->size_in);
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}
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#define cxl_cmd_err(dev, cmd, status, msg) \
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dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \
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(cmd)->opcode, \
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status & CXLMDEV_DEV_FATAL ? " fatal" : "", \
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status & CXLMDEV_FW_HALT ? " firmware-halt" : "")
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/**
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* __cxl_pci_mbox_send_cmd() - Execute a mailbox command
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@ -134,7 +136,11 @@ static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds,
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/* #1 */
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if (cxl_doorbell_busy(cxlds)) {
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dev_err_ratelimited(dev, "Mailbox re-busy after acquiring\n");
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u64 md_status =
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readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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cxl_cmd_err(cxlds->dev, mbox_cmd, md_status,
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"mailbox queue busy");
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return -EBUSY;
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}
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@ -160,7 +166,9 @@ static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds,
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/* #5 */
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rc = cxl_pci_mbox_wait_for_doorbell(cxlds);
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if (rc == -ETIMEDOUT) {
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cxl_pci_mbox_timeout(cxlds, mbox_cmd);
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u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout");
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return rc;
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}
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@ -198,98 +206,13 @@ static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds,
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return 0;
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}
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/**
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* cxl_pci_mbox_get() - Acquire exclusive access to the mailbox.
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* @cxlds: The device state to gain access to.
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*
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* Context: Any context. Takes the mbox_mutex.
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* Return: 0 if exclusive access was acquired.
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*/
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static int cxl_pci_mbox_get(struct cxl_dev_state *cxlds)
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{
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struct device *dev = cxlds->dev;
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u64 md_status;
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int rc;
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mutex_lock_io(&cxlds->mbox_mutex);
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/*
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* XXX: There is some amount of ambiguity in the 2.0 version of the spec
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* around the mailbox interface ready (8.2.8.5.1.1). The purpose of the
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* bit is to allow firmware running on the device to notify the driver
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* that it's ready to receive commands. It is unclear if the bit needs
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* to be read for each transaction mailbox, ie. the firmware can switch
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* it on and off as needed. Second, there is no defined timeout for
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* mailbox ready, like there is for the doorbell interface.
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*
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* Assumptions:
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* 1. The firmware might toggle the Mailbox Interface Ready bit, check
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* it for every command.
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*
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* 2. If the doorbell is clear, the firmware should have first set the
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* Mailbox Interface Ready bit. Therefore, waiting for the doorbell
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* to be ready is sufficient.
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*/
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rc = cxl_pci_mbox_wait_for_doorbell(cxlds);
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if (rc) {
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dev_warn(dev, "Mailbox interface not ready\n");
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goto out;
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}
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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if (!(md_status & CXLMDEV_MBOX_IF_READY && CXLMDEV_READY(md_status))) {
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dev_err(dev, "mbox: reported doorbell ready, but not mbox ready\n");
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rc = -EBUSY;
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goto out;
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}
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/*
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* Hardware shouldn't allow a ready status but also have failure bits
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* set. Spit out an error, this should be a bug report
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*/
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rc = -EFAULT;
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if (md_status & CXLMDEV_DEV_FATAL) {
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dev_err(dev, "mbox: reported ready, but fatal\n");
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goto out;
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}
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if (md_status & CXLMDEV_FW_HALT) {
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dev_err(dev, "mbox: reported ready, but halted\n");
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goto out;
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}
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if (CXLMDEV_RESET_NEEDED(md_status)) {
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dev_err(dev, "mbox: reported ready, but reset needed\n");
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goto out;
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}
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/* with lock held */
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return 0;
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out:
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mutex_unlock(&cxlds->mbox_mutex);
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return rc;
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}
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/**
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* cxl_pci_mbox_put() - Release exclusive access to the mailbox.
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* @cxlds: The device state to communicate with.
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*
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* Context: Any context. Expects mbox_mutex to be held.
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*/
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static void cxl_pci_mbox_put(struct cxl_dev_state *cxlds)
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{
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mutex_unlock(&cxlds->mbox_mutex);
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}
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static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd)
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{
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int rc;
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rc = cxl_pci_mbox_get(cxlds);
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if (rc)
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return rc;
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mutex_lock_io(&cxlds->mbox_mutex);
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rc = __cxl_pci_mbox_send_cmd(cxlds, cmd);
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cxl_pci_mbox_put(cxlds);
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mutex_unlock(&cxlds->mbox_mutex);
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return rc;
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}
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@ -310,11 +233,20 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
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} while (!time_after(jiffies, timeout));
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if (!(md_status & CXLMDEV_MBOX_IF_READY)) {
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dev_err(cxlds->dev,
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"timeout awaiting mailbox ready, device state:%s%s\n",
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md_status & CXLMDEV_DEV_FATAL ? " fatal" : "",
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md_status & CXLMDEV_FW_HALT ? " firmware-halt" : "");
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return -EIO;
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cxl_err(cxlds->dev, md_status,
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"timeout awaiting mailbox ready");
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return -ETIMEDOUT;
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}
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/*
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* A command may be in flight from a previous driver instance,
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* think kexec, do one doorbell wait so that
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* __cxl_pci_mbox_send_cmd() can assume that it is the only
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* source for future doorbell busy events.
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*/
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if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) {
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cxl_err(cxlds->dev, md_status, "timeout awaiting mailbox idle");
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return -ETIMEDOUT;
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}
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cxlds->mbox_send = cxl_pci_mbox_send;
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