misc: cardreader: add new Alcor Micro Cardreader PCI driver
This driver provides support for Alcor Micro AU6601 and AU6621 card readers. This is single LUN HW and it is expected to work with following standards: - Support SDR104 / SDR50 - MultiMedia Card (MMC) - Memory Stick (MS) - Memory Stick PRO (MS_Pro) Since it is a PCIe controller, it should work on any architecture supporting PCIe. For now, it was developed and tested only on x86_64. This driver is a result of RE work and was created without any documentation or real knowledge of HW internals. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Oleksij Rempel
Ulf Hansson
Родитель
8ceb29436c
Коммит
4f556bc04e
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@ -57,4 +57,4 @@ obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
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obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
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obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
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obj-$(CONFIG_OCXL) += ocxl/
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obj-$(CONFIG_MISC_RTSX) += cardreader/
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obj-y += cardreader/
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@ -1,3 +1,14 @@
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config MISC_ALCOR_PCI
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tristate "Alcor Micro/Alcor Link PCI-E card reader"
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depends on PCI
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select MFD_CORE
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help
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This supports for Alcor Micro PCI-Express card reader including au6601,
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au6621.
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Alcor Micro card readers support access to many types of memory cards,
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such as Memory Stick, Memory Stick Pro, Secure Digital and
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MultiMediaCard.
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config MISC_RTSX_PCI
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tristate "Realtek PCI-E card reader"
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depends on PCI
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@ -1,4 +1,4 @@
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o rts5260.o
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obj-$(CONFIG_MISC_ALCOR_PCI) += alcor_pci.o
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obj-$(CONFIG_MISC_RTSX_PCI) += rtsx_pci.o
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o rts5260.o
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obj-$(CONFIG_MISC_RTSX_USB) += rtsx_usb.o
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@ -0,0 +1,371 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
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*
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* Driver for Alcor Micro AU6601 and AU6621 controllers
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/alcor_pci.h>
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#define DRV_NAME_ALCOR_PCI "alcor_pci"
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static DEFINE_IDA(alcor_pci_idr);
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static struct mfd_cell alcor_pci_cells[] = {
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[ALCOR_SD_CARD] = {
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.name = DRV_NAME_ALCOR_PCI_SDMMC,
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},
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[ALCOR_MS_CARD] = {
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.name = DRV_NAME_ALCOR_PCI_MS,
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},
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};
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static const struct alcor_dev_cfg alcor_cfg = {
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.dma = 0,
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};
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static const struct alcor_dev_cfg au6621_cfg = {
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.dma = 1,
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};
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static const struct pci_device_id pci_ids[] = {
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{ PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6601),
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.driver_data = (kernel_ulong_t)&alcor_cfg },
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{ PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6621),
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.driver_data = (kernel_ulong_t)&au6621_cfg },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr)
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{
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writeb(val, priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_write8);
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void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr)
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{
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writew(val, priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_write16);
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void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
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{
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writel(val, priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_write32);
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void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
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{
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iowrite32be(val, priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_write32be);
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u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr)
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{
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return readb(priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_read8);
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u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr)
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{
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return readl(priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_read32);
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u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr)
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{
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return ioread32be(priv->iobase + addr);
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}
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EXPORT_SYMBOL_GPL(alcor_read32be);
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static int alcor_pci_find_cap_offset(struct alcor_pci_priv *priv,
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struct pci_dev *pci)
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{
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int where;
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u8 val8;
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u32 val32;
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where = ALCOR_CAP_START_OFFSET;
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pci_read_config_byte(pci, where, &val8);
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if (!val8)
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return 0;
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where = (int)val8;
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while (1) {
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pci_read_config_dword(pci, where, &val32);
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if (val32 == 0xffffffff) {
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dev_dbg(priv->dev, "find_cap_offset invailid value %x.\n",
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val32);
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return 0;
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}
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if ((val32 & 0xff) == 0x10) {
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dev_dbg(priv->dev, "pcie cap offset: %x\n", where);
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return where;
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}
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if ((val32 & 0xff00) == 0x00) {
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dev_dbg(priv->dev, "pci_find_cap_offset invailid value %x.\n",
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val32);
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break;
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}
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where = (int)((val32 >> 8) & 0xff);
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}
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return 0;
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}
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static void alcor_pci_init_check_aspm(struct alcor_pci_priv *priv)
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{
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struct pci_dev *pci;
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int where;
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u32 val32;
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priv->pdev_cap_off = alcor_pci_find_cap_offset(priv, priv->pdev);
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priv->parent_cap_off = alcor_pci_find_cap_offset(priv,
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priv->parent_pdev);
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if ((priv->pdev_cap_off == 0) || (priv->parent_cap_off == 0)) {
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dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
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priv->pdev_cap_off, priv->parent_cap_off);
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return;
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}
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/* link capability */
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pci = priv->pdev;
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where = priv->pdev_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
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pci_read_config_dword(pci, where, &val32);
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priv->pdev_aspm_cap = (u8)(val32 >> 10) & 0x03;
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pci = priv->parent_pdev;
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where = priv->parent_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
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pci_read_config_dword(pci, where, &val32);
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priv->parent_aspm_cap = (u8)(val32 >> 10) & 0x03;
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if (priv->pdev_aspm_cap != priv->parent_aspm_cap) {
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u8 aspm_cap;
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dev_dbg(priv->dev, "pdev_aspm_cap: %x, parent_aspm_cap: %x\n",
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priv->pdev_aspm_cap, priv->parent_aspm_cap);
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aspm_cap = priv->pdev_aspm_cap & priv->parent_aspm_cap;
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priv->pdev_aspm_cap = aspm_cap;
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priv->parent_aspm_cap = aspm_cap;
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}
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dev_dbg(priv->dev, "ext_config_dev_aspm: %x, pdev_aspm_cap: %x\n",
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priv->ext_config_dev_aspm, priv->pdev_aspm_cap);
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priv->ext_config_dev_aspm &= priv->pdev_aspm_cap;
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}
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static void alcor_pci_aspm_ctrl(struct alcor_pci_priv *priv, u8 aspm_enable)
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{
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struct pci_dev *pci;
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u8 aspm_ctrl, i;
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int where;
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u32 val32;
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if ((!priv->pdev_cap_off) || (!priv->parent_cap_off)) {
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dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
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priv->pdev_cap_off, priv->parent_cap_off);
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return;
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}
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if (!priv->pdev_aspm_cap)
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return;
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aspm_ctrl = 0;
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if (aspm_enable) {
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aspm_ctrl = priv->ext_config_dev_aspm;
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if (!aspm_ctrl) {
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dev_dbg(priv->dev, "aspm_ctrl == 0\n");
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return;
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}
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}
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for (i = 0; i < 2; i++) {
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if (i) {
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pci = priv->parent_pdev;
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where = priv->parent_cap_off
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+ ALCOR_PCIE_LINK_CTRL_OFFSET;
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} else {
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pci = priv->pdev;
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where = priv->pdev_cap_off
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+ ALCOR_PCIE_LINK_CTRL_OFFSET;
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}
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pci_read_config_dword(pci, where, &val32);
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val32 &= (~0x03);
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val32 |= (aspm_ctrl & priv->pdev_aspm_cap);
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pci_write_config_byte(pci, where, (u8)val32);
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}
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}
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static inline void alcor_mask_sd_irqs(struct alcor_pci_priv *priv)
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{
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alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
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}
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static inline void alcor_unmask_sd_irqs(struct alcor_pci_priv *priv)
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{
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alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
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AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
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AU6601_INT_OVER_CURRENT_ERR,
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AU6601_REG_INT_ENABLE);
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}
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static inline void alcor_mask_ms_irqs(struct alcor_pci_priv *priv)
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{
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alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
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}
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static inline void alcor_unmask_ms_irqs(struct alcor_pci_priv *priv)
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{
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alcor_write32(priv, 0x3d00fa, AU6601_MS_INT_ENABLE);
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}
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static int alcor_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct alcor_dev_cfg *cfg;
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struct alcor_pci_priv *priv;
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int ret, i, bar = 0;
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cfg = (void *)ent->driver_data;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ret = ida_simple_get(&alcor_pci_idr, 0, 0, GFP_KERNEL);
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if (ret < 0)
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return ret;
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priv->id = ret;
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priv->pdev = pdev;
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priv->parent_pdev = pdev->bus->self;
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priv->dev = &pdev->dev;
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priv->cfg = cfg;
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priv->irq = pdev->irq;
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ret = pci_request_regions(pdev, DRV_NAME_ALCOR_PCI);
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if (ret) {
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dev_err(&pdev->dev, "Cannot request region\n");
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return -ENOMEM;
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}
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if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
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dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
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ret = -ENODEV;
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goto error_release_regions;
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}
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priv->iobase = pcim_iomap(pdev, bar, 0);
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if (!priv->iobase) {
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ret = -ENOMEM;
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goto error_release_regions;
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}
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/* make sure irqs are disabled */
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alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
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alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
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ret = dma_set_mask_and_coherent(priv->dev, AU6601_SDMA_MASK);
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if (ret) {
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dev_err(priv->dev, "Failed to set DMA mask\n");
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goto error_release_regions;
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}
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pci_set_master(pdev);
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pci_set_drvdata(pdev, priv);
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alcor_pci_init_check_aspm(priv);
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for (i = 0; i < ARRAY_SIZE(alcor_pci_cells); i++) {
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alcor_pci_cells[i].platform_data = priv;
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alcor_pci_cells[i].pdata_size = sizeof(*priv);
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}
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ret = mfd_add_devices(&pdev->dev, priv->id, alcor_pci_cells,
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ARRAY_SIZE(alcor_pci_cells), NULL, 0, NULL);
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if (ret < 0)
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goto error_release_regions;
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alcor_pci_aspm_ctrl(priv, 0);
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return 0;
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error_release_regions:
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pci_release_regions(pdev);
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return ret;
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}
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static void alcor_pci_remove(struct pci_dev *pdev)
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{
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struct alcor_pci_priv *priv;
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priv = pci_get_drvdata(pdev);
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alcor_pci_aspm_ctrl(priv, 1);
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mfd_remove_devices(&pdev->dev);
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ida_simple_remove(&alcor_pci_idr, priv->id);
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pci_release_regions(pdev);
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pci_set_drvdata(pdev, NULL);
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}
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#ifdef CONFIG_PM_SLEEP
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static int alcor_suspend(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct alcor_pci_priv *priv = pci_get_drvdata(pdev);
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alcor_pci_aspm_ctrl(priv, 1);
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return 0;
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}
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static int alcor_resume(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct alcor_pci_priv *priv = pci_get_drvdata(pdev);
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alcor_pci_aspm_ctrl(priv, 0);
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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static SIMPLE_DEV_PM_OPS(alcor_pci_pm_ops, alcor_suspend, alcor_resume);
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static struct pci_driver alcor_driver = {
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.name = DRV_NAME_ALCOR_PCI,
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.id_table = pci_ids,
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.probe = alcor_pci_probe,
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.remove = alcor_pci_remove,
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.driver = {
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.pm = &alcor_pci_pm_ops
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},
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};
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module_pci_driver(alcor_driver);
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MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
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MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
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MODULE_LICENSE("GPL");
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@ -0,0 +1,286 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
|
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* Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
|
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*
|
||||
* Driver for Alcor Micro AU6601 and AU6621 controllers
|
||||
*/
|
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|
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#ifndef __ALCOR_PCI_H
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#define __ALCOR_PCI_H
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#define ALCOR_SD_CARD 0
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#define ALCOR_MS_CARD 1
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#define DRV_NAME_ALCOR_PCI_SDMMC "alcor_sdmmc"
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#define DRV_NAME_ALCOR_PCI_MS "alcor_ms"
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#define PCI_ID_ALCOR_MICRO 0x1AEA
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#define PCI_ID_AU6601 0x6601
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#define PCI_ID_AU6621 0x6621
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#define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
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#define AU6601_BASE_CLOCK 31000000
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#define AU6601_MIN_CLOCK 150000
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#define AU6601_MAX_CLOCK 208000000
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#define AU6601_MAX_DMA_SEGMENTS 1
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#define AU6601_MAX_PIO_SEGMENTS 1
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#define AU6601_MAX_DMA_BLOCK_SIZE 0x1000
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#define AU6601_MAX_PIO_BLOCK_SIZE 0x200
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#define AU6601_MAX_DMA_BLOCKS 1
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#define AU6601_DMA_LOCAL_SEGMENTS 1
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/* registers spotter by reverse engineering but still
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||||
* with unknown functionality:
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* 0x10 - ADMA phy address. AU6621 only?
|
||||
* 0x51 - LED ctrl?
|
||||
* 0x52 - unknown
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* 0x61 - LED related? Always toggled BIT0
|
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* 0x63 - Same as 0x61?
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||||
* 0x77 - unknown
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||||
*/
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||||
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||||
/* SDMA phy address. Higher then 0x0800.0000?
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||||
* The au6601 and au6621 have different DMA engines with different issues. One
|
||||
* For example au6621 engine is triggered by addr change. No other interaction
|
||||
* is needed. This means, if we get two buffers with same address, then engine
|
||||
* will stall.
|
||||
*/
|
||||
#define AU6601_REG_SDMA_ADDR 0x00
|
||||
#define AU6601_SDMA_MASK 0xffffffff
|
||||
|
||||
#define AU6601_DMA_BOUNDARY 0x05
|
||||
#define AU6621_DMA_PAGE_CNT 0x05
|
||||
/* PIO */
|
||||
#define AU6601_REG_BUFFER 0x08
|
||||
/* ADMA ctrl? AU6621 only. */
|
||||
#define AU6621_DMA_CTRL 0x0c
|
||||
#define AU6621_DMA_ENABLE BIT(0)
|
||||
/* CMD index */
|
||||
#define AU6601_REG_CMD_OPCODE 0x23
|
||||
/* CMD parametr */
|
||||
#define AU6601_REG_CMD_ARG 0x24
|
||||
/* CMD response 4x4 Bytes */
|
||||
#define AU6601_REG_CMD_RSP0 0x30
|
||||
#define AU6601_REG_CMD_RSP1 0x34
|
||||
#define AU6601_REG_CMD_RSP2 0x38
|
||||
#define AU6601_REG_CMD_RSP3 0x3C
|
||||
/* default timeout set to 125: 125 * 40ms = 5 sec
|
||||
* how exactly it is calculated?
|
||||
*/
|
||||
#define AU6601_TIME_OUT_CTRL 0x69
|
||||
/* Block size for SDMA or PIO */
|
||||
#define AU6601_REG_BLOCK_SIZE 0x6c
|
||||
/* Some power related reg, used together with AU6601_OUTPUT_ENABLE */
|
||||
#define AU6601_POWER_CONTROL 0x70
|
||||
|
||||
/* PLL ctrl */
|
||||
#define AU6601_CLK_SELECT 0x72
|
||||
#define AU6601_CLK_OVER_CLK 0x80
|
||||
#define AU6601_CLK_384_MHZ 0x30
|
||||
#define AU6601_CLK_125_MHZ 0x20
|
||||
#define AU6601_CLK_48_MHZ 0x10
|
||||
#define AU6601_CLK_EXT_PLL 0x04
|
||||
#define AU6601_CLK_X2_MODE 0x02
|
||||
#define AU6601_CLK_ENABLE 0x01
|
||||
#define AU6601_CLK_31_25_MHZ 0x00
|
||||
|
||||
#define AU6601_CLK_DIVIDER 0x73
|
||||
|
||||
#define AU6601_INTERFACE_MODE_CTRL 0x74
|
||||
#define AU6601_DLINK_MODE 0x80
|
||||
#define AU6601_INTERRUPT_DELAY_TIME 0x40
|
||||
#define AU6601_SIGNAL_REQ_CTRL 0x30
|
||||
#define AU6601_MS_CARD_WP BIT(3)
|
||||
#define AU6601_SD_CARD_WP BIT(0)
|
||||
|
||||
/* same register values are used for:
|
||||
* - AU6601_OUTPUT_ENABLE
|
||||
* - AU6601_POWER_CONTROL
|
||||
*/
|
||||
#define AU6601_ACTIVE_CTRL 0x75
|
||||
#define AU6601_XD_CARD BIT(4)
|
||||
/* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */
|
||||
#define AU6601_MS_CARD BIT(3)
|
||||
#define AU6601_SD_CARD BIT(0)
|
||||
|
||||
/* card slot state. It should automatically detect type of
|
||||
* the card
|
||||
*/
|
||||
#define AU6601_DETECT_STATUS 0x76
|
||||
#define AU6601_DETECT_EN BIT(7)
|
||||
#define AU6601_MS_DETECTED BIT(3)
|
||||
#define AU6601_SD_DETECTED BIT(0)
|
||||
#define AU6601_DETECT_STATUS_M 0xf
|
||||
|
||||
#define AU6601_REG_SW_RESET 0x79
|
||||
#define AU6601_BUF_CTRL_RESET BIT(7)
|
||||
#define AU6601_RESET_DATA BIT(3)
|
||||
#define AU6601_RESET_CMD BIT(0)
|
||||
|
||||
#define AU6601_OUTPUT_ENABLE 0x7a
|
||||
|
||||
#define AU6601_PAD_DRIVE0 0x7b
|
||||
#define AU6601_PAD_DRIVE1 0x7c
|
||||
#define AU6601_PAD_DRIVE2 0x7d
|
||||
/* read EEPROM? */
|
||||
#define AU6601_FUNCTION 0x7f
|
||||
|
||||
#define AU6601_CMD_XFER_CTRL 0x81
|
||||
#define AU6601_CMD_17_BYTE_CRC 0xc0
|
||||
#define AU6601_CMD_6_BYTE_WO_CRC 0x80
|
||||
#define AU6601_CMD_6_BYTE_CRC 0x40
|
||||
#define AU6601_CMD_START_XFER 0x20
|
||||
#define AU6601_CMD_STOP_WAIT_RDY 0x10
|
||||
#define AU6601_CMD_NO_RESP 0x00
|
||||
|
||||
#define AU6601_REG_BUS_CTRL 0x82
|
||||
#define AU6601_BUS_WIDTH_4BIT 0x20
|
||||
#define AU6601_BUS_WIDTH_8BIT 0x10
|
||||
#define AU6601_BUS_WIDTH_1BIT 0x00
|
||||
|
||||
#define AU6601_DATA_XFER_CTRL 0x83
|
||||
#define AU6601_DATA_WRITE BIT(7)
|
||||
#define AU6601_DATA_DMA_MODE BIT(6)
|
||||
#define AU6601_DATA_START_XFER BIT(0)
|
||||
|
||||
#define AU6601_DATA_PIN_STATE 0x84
|
||||
#define AU6601_BUS_STAT_CMD BIT(15)
|
||||
/* BIT(4) - BIT(7) are permanently 1.
|
||||
* May be reserved or not attached DAT4-DAT7
|
||||
*/
|
||||
#define AU6601_BUS_STAT_DAT3 BIT(3)
|
||||
#define AU6601_BUS_STAT_DAT2 BIT(2)
|
||||
#define AU6601_BUS_STAT_DAT1 BIT(1)
|
||||
#define AU6601_BUS_STAT_DAT0 BIT(0)
|
||||
#define AU6601_BUS_STAT_DAT_MASK 0xf
|
||||
|
||||
#define AU6601_OPT 0x85
|
||||
#define AU6601_OPT_CMD_LINE_LEVEL 0x80
|
||||
#define AU6601_OPT_NCRC_16_CLK BIT(4)
|
||||
#define AU6601_OPT_CMD_NWT BIT(3)
|
||||
#define AU6601_OPT_STOP_CLK BIT(2)
|
||||
#define AU6601_OPT_DDR_MODE BIT(1)
|
||||
#define AU6601_OPT_SD_18V BIT(0)
|
||||
|
||||
#define AU6601_CLK_DELAY 0x86
|
||||
#define AU6601_CLK_DATA_POSITIVE_EDGE 0x80
|
||||
#define AU6601_CLK_CMD_POSITIVE_EDGE 0x40
|
||||
#define AU6601_CLK_POSITIVE_EDGE_ALL (AU6601_CLK_CMD_POSITIVE_EDGE \
|
||||
| AU6601_CLK_DATA_POSITIVE_EDGE)
|
||||
|
||||
|
||||
#define AU6601_REG_INT_STATUS 0x90
|
||||
#define AU6601_REG_INT_ENABLE 0x94
|
||||
#define AU6601_INT_DATA_END_BIT_ERR BIT(22)
|
||||
#define AU6601_INT_DATA_CRC_ERR BIT(21)
|
||||
#define AU6601_INT_DATA_TIMEOUT_ERR BIT(20)
|
||||
#define AU6601_INT_CMD_INDEX_ERR BIT(19)
|
||||
#define AU6601_INT_CMD_END_BIT_ERR BIT(18)
|
||||
#define AU6601_INT_CMD_CRC_ERR BIT(17)
|
||||
#define AU6601_INT_CMD_TIMEOUT_ERR BIT(16)
|
||||
#define AU6601_INT_ERROR BIT(15)
|
||||
#define AU6601_INT_OVER_CURRENT_ERR BIT(8)
|
||||
#define AU6601_INT_CARD_INSERT BIT(7)
|
||||
#define AU6601_INT_CARD_REMOVE BIT(6)
|
||||
#define AU6601_INT_READ_BUF_RDY BIT(5)
|
||||
#define AU6601_INT_WRITE_BUF_RDY BIT(4)
|
||||
#define AU6601_INT_DMA_END BIT(3)
|
||||
#define AU6601_INT_DATA_END BIT(1)
|
||||
#define AU6601_INT_CMD_END BIT(0)
|
||||
|
||||
#define AU6601_INT_NORMAL_MASK 0x00007FFF
|
||||
#define AU6601_INT_ERROR_MASK 0xFFFF8000
|
||||
|
||||
#define AU6601_INT_CMD_MASK (AU6601_INT_CMD_END | \
|
||||
AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \
|
||||
AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR)
|
||||
#define AU6601_INT_DATA_MASK (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \
|
||||
AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \
|
||||
AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \
|
||||
AU6601_INT_DATA_END_BIT_ERR)
|
||||
#define AU6601_INT_ALL_MASK ((u32)-1)
|
||||
|
||||
/* MS_CARD mode registers */
|
||||
|
||||
#define AU6601_MS_STATUS 0xa0
|
||||
|
||||
#define AU6601_MS_BUS_MODE_CTRL 0xa1
|
||||
#define AU6601_MS_BUS_8BIT_MODE 0x03
|
||||
#define AU6601_MS_BUS_4BIT_MODE 0x01
|
||||
#define AU6601_MS_BUS_1BIT_MODE 0x00
|
||||
|
||||
#define AU6601_MS_TPC_CMD 0xa2
|
||||
#define AU6601_MS_TPC_READ_PAGE_DATA 0x02
|
||||
#define AU6601_MS_TPC_READ_REG 0x04
|
||||
#define AU6601_MS_TPC_GET_INT 0x07
|
||||
#define AU6601_MS_TPC_WRITE_PAGE_DATA 0x0D
|
||||
#define AU6601_MS_TPC_WRITE_REG 0x0B
|
||||
#define AU6601_MS_TPC_SET_RW_REG_ADRS 0x08
|
||||
#define AU6601_MS_TPC_SET_CMD 0x0E
|
||||
#define AU6601_MS_TPC_EX_SET_CMD 0x09
|
||||
#define AU6601_MS_TPC_READ_SHORT_DATA 0x03
|
||||
#define AU6601_MS_TPC_WRITE_SHORT_DATA 0x0C
|
||||
|
||||
#define AU6601_MS_TRANSFER_MODE 0xa3
|
||||
#define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2)
|
||||
#define AU6601_MS_XFER_DMA_ENABLE BIT(1)
|
||||
#define AU6601_MS_XFER_START BIT(0)
|
||||
|
||||
#define AU6601_MS_DATA_PIN_STATE 0xa4
|
||||
|
||||
#define AU6601_MS_INT_STATUS 0xb0
|
||||
#define AU6601_MS_INT_ENABLE 0xb4
|
||||
#define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23)
|
||||
#define AU6601_MS_INT_DATA_CRC_ERROR BIT(21)
|
||||
#define AU6601_MS_INT_INT_TIMEOUT BIT(20)
|
||||
#define AU6601_MS_INT_INT_RESP_ERROR BIT(19)
|
||||
#define AU6601_MS_INT_CED_ERROR BIT(18)
|
||||
#define AU6601_MS_INT_TPC_TIMEOUT BIT(16)
|
||||
#define AU6601_MS_INT_ERROR BIT(15)
|
||||
#define AU6601_MS_INT_CARD_INSERT BIT(7)
|
||||
#define AU6601_MS_INT_CARD_REMOVE BIT(6)
|
||||
#define AU6601_MS_INT_BUF_READ_RDY BIT(5)
|
||||
#define AU6601_MS_INT_BUF_WRITE_RDY BIT(4)
|
||||
#define AU6601_MS_INT_DMA_END BIT(3)
|
||||
#define AU6601_MS_INT_TPC_END BIT(1)
|
||||
|
||||
#define AU6601_MS_INT_DATA_MASK 0x00000038
|
||||
#define AU6601_MS_INT_TPC_MASK 0x003d8002
|
||||
#define AU6601_MS_INT_TPC_ERROR 0x003d0000
|
||||
|
||||
#define ALCOR_PCIE_LINK_CTRL_OFFSET 0x10
|
||||
#define ALCOR_PCIE_LINK_CAP_OFFSET 0x0c
|
||||
#define ALCOR_CAP_START_OFFSET 0x34
|
||||
|
||||
struct alcor_dev_cfg {
|
||||
u8 dma;
|
||||
};
|
||||
|
||||
struct alcor_pci_priv {
|
||||
struct pci_dev *pdev;
|
||||
struct pci_dev *parent_pdev;
|
||||
struct device *dev;
|
||||
void __iomem *iobase;
|
||||
unsigned int irq;
|
||||
|
||||
unsigned long id; /* idr id */
|
||||
|
||||
struct alcor_dev_cfg *cfg;
|
||||
|
||||
/* PCI ASPM related vars */
|
||||
int pdev_cap_off;
|
||||
u8 pdev_aspm_cap;
|
||||
int parent_cap_off;
|
||||
u8 parent_aspm_cap;
|
||||
u8 ext_config_dev_aspm;
|
||||
};
|
||||
|
||||
void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr);
|
||||
void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr);
|
||||
void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
|
||||
void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
|
||||
u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr);
|
||||
u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr);
|
||||
u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr);
|
||||
#endif
|
||||
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