media: dvb-frontends/stv0910: cosmetics: fixup comments, misc
Fix up block comment style, whitespaces, c++ style comments et al. Signed-off-by: Daniel Scheller <d.scheller@gmx.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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@ -207,7 +207,7 @@ static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
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return status;
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}
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struct slookup s1_sn_lookup[] = {
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static struct slookup s1_sn_lookup[] = {
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{ 0, 9242 }, /* C/N= 0dB */
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{ 5, 9105 }, /* C/N= 0.5dB */
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{ 10, 8950 }, /* C/N= 1.0dB */
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@ -264,7 +264,7 @@ struct slookup s1_sn_lookup[] = {
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{ 510, 425 } /* C/N=51.0dB */
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};
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struct slookup s2_sn_lookup[] = {
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static struct slookup s2_sn_lookup[] = {
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{ -30, 13950 }, /* C/N=-2.5dB */
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{ -25, 13580 }, /* C/N=-2.5dB */
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{ -20, 13150 }, /* C/N=-2.0dB */
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@ -327,7 +327,7 @@ struct slookup s2_sn_lookup[] = {
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{ 510, 463 }, /* C/N=51.0dB */
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};
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struct slookup padc_lookup[] = {
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static struct slookup padc_lookup[] = {
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{ 0, 118000 }, /* PADC= +0dBm */
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{ -100, 93600 }, /* PADC= -1dBm */
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{ -200, 74500 }, /* PADC= -2dBm */
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@ -350,7 +350,8 @@ struct slookup padc_lookup[] = {
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* Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
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*********************************************************************/
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static u8 s2car_loop[] = {
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/* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
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/*
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* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
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* 20MPon 20MPoff 30MPon 30MPoff
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*/
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@ -393,7 +394,8 @@ static u8 s2car_loop[] = {
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* Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
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**********************************************************************/
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/* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
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/*
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* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
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* 20MPoff 30MPon 30MPoff
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*/
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@ -870,38 +872,38 @@ static int init_search_param(struct stv *state)
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u8 tmp;
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read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
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tmp |= 0x20; // Filter_en (no effect if SIS=non-MIS
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tmp |= 0x20; /* Filter_en (no effect if SIS=non-MIS */
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write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, &tmp);
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tmp &= ~0x02; // frame mode = 0
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tmp &= ~0x02; /* frame mode = 0 */
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write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, tmp);
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write_reg(state, RSTV0910_P2_UPLCCST0 + state->regoff, 0xe0);
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write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0x00);
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read_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, &tmp);
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tmp &= ~0x01; // nosync = 0, in case next signal is standard TS
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tmp &= ~0x01; /* nosync = 0, in case next signal is standard TS */
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write_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_TSCFGL + state->regoff, &tmp);
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tmp &= ~0x04; // embindvb = 0
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tmp &= ~0x04; /* embindvb = 0 */
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write_reg(state, RSTV0910_P2_TSCFGL + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, &tmp);
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tmp &= ~0x80; // syncbyte = 0
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tmp &= ~0x80; /* syncbyte = 0 */
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write_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, &tmp);
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tmp &= ~0x08; // token = 0
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tmp &= ~0x08; /* token = 0 */
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write_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, &tmp);
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tmp &= ~0x30; // hysteresis threshold = 0
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tmp &= ~0x30; /* hysteresis threshold = 0 */
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write_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, tmp);
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read_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, &tmp);
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tmp = (tmp & ~0x30) | 0x10; // isi obs mode = 1, observe min ISI
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tmp = (tmp & ~0x30) | 0x10; /* isi obs mode = 1, observe min ISI */
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write_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, tmp);
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return 0;
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@ -1001,7 +1003,8 @@ static int start(struct stv *state, struct dtv_frontend_properties *p)
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init_search_param(state);
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if (p->stream_id != NO_STREAM_ID_FILTER) {
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/* Backwards compatibility to "crazy" API.
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/*
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* Backwards compatibility to "crazy" API.
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* PRBS X root cannot be 0, so this should always work.
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*/
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if (p->stream_id & 0xffffff00)
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@ -1078,8 +1081,10 @@ static int start(struct stv *state, struct dtv_frontend_properties *p)
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write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
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write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
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/* Reset CAR3, bug DVBS2->DVBS1 lock*/
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/* Note: The bit is only pulsed -> no lock on shared register needed */
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/*
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* Reset CAR3, bug DVBS2->DVBS1 lock
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* Note: The bit is only pulsed -> no lock on shared register needed
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*/
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write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
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write_reg(state, RSTV0910_TSTRES0, 0);
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@ -1425,7 +1430,8 @@ static int read_status(struct dvb_frontend *fe, enum fe_status *status)
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manage_matype_info(state);
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if (state->receive_mode == RCVMODE_DVBS2) {
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/* FSTV0910_P2_MANUALSX_ROLLOFF,
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/*
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* FSTV0910_P2_MANUALSX_ROLLOFF,
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* FSTV0910_P2_MANUALS2_ROLLOFF = 0
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*/
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state->demod_bits &= ~0x84;
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@ -1465,7 +1471,8 @@ static int read_status(struct dvb_frontend *fe, enum fe_status *status)
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/* Reset the Total packet counter */
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write_reg(state,
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RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
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/* Reset the packet Error counter2 (and Set it to
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/*
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* Reset the packet Error counter2 (and Set it to
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* infinit error count mode)
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*/
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write_reg(state,
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@ -1,4 +1,5 @@
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/* @DVB-S/DVB-S2 STMicroelectronics STV0900 register definitions
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/*
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* @DVB-S/DVB-S2 STMicroelectronics STV0900 register definitions
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* Author Manfred Voelkel, August 2013
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* (c) 2013 Digital Devices GmbH Germany. All rights reserved
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*
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