ath5k: Correct usage of AR5K_CFG_ADHOC
This corrects usage of AR5K_CFG_ADHOC introduced in "ath5k: Update PCU code". Also, the name of the indicator is changed to AR5K_CFG_IBSS to more accurately reflect its function. This change restores beaconing in AP and mesh modes. Signed-off-by: Steve Brown <sbrown@cortland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Родитель
157ec87684
Коммит
4fb7404e0e
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@ -65,7 +65,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
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if (ah->ah_version == AR5K_AR5210)
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pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
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else
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AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
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AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
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break;
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case NL80211_IFTYPE_AP:
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@ -75,7 +75,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
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if (ah->ah_version == AR5K_AR5210)
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pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
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else
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AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
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AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
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break;
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case NL80211_IFTYPE_STATION:
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@ -73,7 +73,7 @@
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#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
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#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
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#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
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#define AR5K_CFG_ADHOC 0x00000020 /* AP/Adhoc indication [5211+] */
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#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
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#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
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#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
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#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
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