arm: Xilinx Zynq cleanup patches for v3.16
- Add support for BIG Endian - Add SOC_BUS support - Sort Kconfig options - Fix early console -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlOCxdwACgkQykllyylKDCEydwCglWoRgU1kvPH6oqyH5esHv7L3 oY4AnA+t3msa91ovFFbsCm2xW77QbbC6 =Ubf9 -----END PGP SIGNATURE----- Merge tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx into next/soc Merge "Xilinx Zynq changes for v3.16" from Michal Simek: arm: Xilinx Zynq cleanup patches for v3.16 - Add support for BIG Endian - Add SOC_BUS support - Sort Kconfig options - Fix early console * tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Enable big-endian ARM: zynq: Fix uart0 early console virtual address clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw ARM: zynq: Sort Kconfig options ARM: zynq: Add support for SOC_BUS Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
4fd0912044
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@ -177,6 +177,11 @@
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};
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};
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devcfg: devcfg@f8007000 {
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compatible = "xlnx,zynq-devcfg-1.0";
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reg = <0xf8007000 0x100>;
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} ;
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global_timer: timer@f8f00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xf8f00200 0x20>;
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@ -20,18 +20,18 @@
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#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
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#define UART0_PHYS 0xE0000000
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#define UART0_VIRT 0xF0000000
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#define UART1_PHYS 0xE0001000
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#define UART_SIZE SZ_4K
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#define UART_VIRT 0xF0001000
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#define UART1_VIRT 0xF0001000
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#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
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# define LL_UART_PADDR UART1_PHYS
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# define LL_UART_VADDR UART1_VIRT
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#else
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# define LL_UART_PADDR UART0_PHYS
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# define LL_UART_VADDR UART0_VIRT
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#endif
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#define LL_UART_VADDR UART_VIRT
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.macro addruart, rp, rv, tmp
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ldr \rp, =LL_UART_PADDR @ physical
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ldr \rv, =LL_UART_VADDR @ virtual
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@ -43,12 +43,14 @@
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #UART_SR_OFFSET]
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXEMPTY
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXFULL @
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bne 1002b @ wait if FIFO is full
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.endm
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@ -1,14 +1,16 @@
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config ARCH_ZYNQ
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bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
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select ARM_AMBA
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select ARM_GIC
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select ARCH_HAS_CPUFREQ
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select ARCH_HAS_OPP
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select ARM_GLOBAL_TIMER if !CPU_FREQ
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select CADENCE_TTC_TIMER
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select ICST
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select CADENCE_TTC_TIMER
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select ARM_GLOBAL_TIMER if !CPU_FREQ
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select MFD_SYSCON
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select SOC_BUS
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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@ -29,6 +29,8 @@
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#include <linux/memblock.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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@ -37,10 +39,15 @@
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/smp_scu.h>
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#include <asm/system_info.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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#define ZYNQ_DEVCFG_MCTRL 0x80
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#define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28
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#define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
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void __iomem *zynq_scu_base;
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/**
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@ -59,6 +66,38 @@ static struct platform_device zynq_cpuidle_device = {
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.name = "cpuidle-zynq",
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};
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/**
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* zynq_get_revision - Get Zynq silicon revision
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*
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* Return: Silicon version or -1 otherwise
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*/
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static int __init zynq_get_revision(void)
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{
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struct device_node *np;
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void __iomem *zynq_devcfg_base;
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u32 revision;
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np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
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if (!np) {
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pr_err("%s: no devcfg node found\n", __func__);
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return -1;
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}
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zynq_devcfg_base = of_iomap(np, 0);
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if (!zynq_devcfg_base) {
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pr_err("%s: Unable to map I/O memory\n", __func__);
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return -1;
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}
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revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
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revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
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revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
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iounmap(zynq_devcfg_base);
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return revision;
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}
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/**
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* zynq_init_machine - System specific initialization, intended to be
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* called from board specific initialization.
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@ -66,13 +105,43 @@ static struct platform_device zynq_cpuidle_device = {
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static void __init zynq_init_machine(void)
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{
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struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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struct device *parent = NULL;
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/*
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* 64KB way size, 8-way associativity, parity disabled
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*/
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l2x0_of_init(0x02060000, 0xF0F0FFFF);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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goto out;
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system_rev = zynq_get_revision();
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soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
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soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
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zynq_slcr_get_device_id());
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->family);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr->soc_id);
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kfree(soc_dev_attr);
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goto out;
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}
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parent = soc_device_to_device(soc_dev);
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out:
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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platform_device_register(&zynq_cpuidle_device);
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platform_device_register_full(&devinfo);
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@ -24,6 +24,7 @@ extern int zynq_early_slcr_init(void);
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extern void zynq_slcr_system_reset(void);
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extern void zynq_slcr_cpu_stop(int cpu);
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extern void zynq_slcr_cpu_start(int cpu);
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extern u32 zynq_slcr_get_device_id(void);
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#ifdef CONFIG_SMP
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extern void secondary_startup(void);
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@ -8,9 +8,12 @@
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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ENTRY(zynq_secondary_trampoline)
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ldr r0, [pc]
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ARM_BE8(setend be) @ ensure we are in BE8 mode
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ldr r0, zynq_secondary_trampoline_jump
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ARM_BE8(rev r0, r0)
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bx r0
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.globl zynq_secondary_trampoline_jump
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zynq_secondary_trampoline_jump:
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@ -26,10 +26,13 @@
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
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#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
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#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
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static void __iomem *zynq_slcr_base;
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static struct regmap *zynq_slcr_regmap;
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@ -82,6 +85,22 @@ static inline int zynq_slcr_unlock(void)
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return 0;
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}
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/**
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* zynq_slcr_get_device_id - Read device code id
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*
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* Return: Device code id
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*/
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u32 zynq_slcr_get_device_id(void)
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{
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u32 val;
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zynq_slcr_read(&val, SLCR_PSS_IDCODE);
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val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
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val &= SLCR_PSS_IDCODE_DEVICE_MASK;
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return val;
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}
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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*/
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@ -118,11 +118,11 @@ static void ttc_set_interval(struct ttc_timer *timer,
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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/*
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* Reset the counter (0x10) so that it starts from 0, one-shot
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@ -130,7 +130,7 @@ static void ttc_set_interval(struct ttc_timer *timer,
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*/
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ctrl_reg |= CNT_CNTRL_RESET;
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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}
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/**
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@ -147,7 +147,7 @@ static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
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struct ttc_timer *timer = &ttce->ttc;
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/* Acknowledge the interrupt and call event handler */
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__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
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readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
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ttce->ce.event_handler(&ttce->ce);
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@ -163,13 +163,13 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
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{
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struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
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return (cycle_t)__raw_readl(timer->base_addr +
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return (cycle_t)readl_relaxed(timer->base_addr +
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TTC_COUNT_VAL_OFFSET);
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}
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static u64 notrace ttc_sched_clock_read(void)
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{
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return __raw_readl(ttc_sched_clock_val_reg);
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return readl_relaxed(ttc_sched_clock_val_reg);
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}
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/**
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@ -211,17 +211,17 @@ static void ttc_set_mode(enum clock_event_mode mode,
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl_reg = __raw_readl(timer->base_addr +
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ctrl_reg = readl_relaxed(timer->base_addr +
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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writel_relaxed(ctrl_reg,
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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case CLOCK_EVT_MODE_RESUME:
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ctrl_reg = __raw_readl(timer->base_addr +
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ctrl_reg = readl_relaxed(timer->base_addr +
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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writel_relaxed(ctrl_reg,
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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}
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@ -266,8 +266,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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* of an abort.
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*/
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ttccs->scale_clk_ctrl_reg_old =
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__raw_readl(ttccs->ttc.base_addr +
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TTC_CLK_CNTRL_OFFSET);
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readl_relaxed(ttccs->ttc.base_addr +
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TTC_CLK_CNTRL_OFFSET);
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psv = (ttccs->scale_clk_ctrl_reg_old &
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TTC_CLK_CNTRL_PSV_MASK) >>
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@ -291,8 +291,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_DONE;
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/* scale up: adjust divider now - before frequency change */
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__raw_writel(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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}
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case POST_RATE_CHANGE:
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@ -301,8 +301,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_OK;
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/* scale down: adjust divider now - after frequency change */
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__raw_writel(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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case ABORT_RATE_CHANGE:
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@ -311,8 +311,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_OK;
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/* restore original register value */
|
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__raw_writel(ttccs->scale_clk_ctrl_reg_old,
|
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
|
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writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
|
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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/* fall through */
|
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default:
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return NOTIFY_DONE;
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|
|
@ -359,10 +359,10 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
|
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* it by 32 also. Let it start running now.
|
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*/
|
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__raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
|
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
|
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writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
|
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
|
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
|
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__raw_writel(CNT_CNTRL_RESET,
|
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writel_relaxed(CNT_CNTRL_RESET,
|
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ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
|
||||
|
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err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
|
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|
|
@ -438,10 +438,10 @@ static void __init ttc_setup_clockevent(struct clk *clk,
|
|||
* is prescaled by 32 using the interval interrupt. Leave it
|
||||
* disabled for now.
|
||||
*/
|
||||
__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
|
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
|
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writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
|
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
|
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ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
|
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__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
|
||||
writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
|
||||
|
||||
err = request_irq(irq, ttc_clock_event_interrupt,
|
||||
IRQF_TIMER, ttcce->ce.name, ttcce);
|
||||
|
|
@ -490,7 +490,7 @@ static void __init ttc_timer_init(struct device_node *timer)
|
|||
BUG();
|
||||
}
|
||||
|
||||
clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
|
||||
clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
|
||||
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
|
||||
clk_cs = of_clk_get(timer, clksel);
|
||||
if (IS_ERR(clk_cs)) {
|
||||
|
|
@ -498,7 +498,7 @@ static void __init ttc_timer_init(struct device_node *timer)
|
|||
BUG();
|
||||
}
|
||||
|
||||
clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
|
||||
clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
|
||||
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
|
||||
clk_ce = of_clk_get(timer, clksel);
|
||||
if (IS_ERR(clk_ce)) {
|
||||
|
|
|
|||
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Ссылка в новой задаче