mmc: bfin_sdh: Add support for new RSI controller in bf60x
In BF60x RSI controller: 1) MMR read/write width differs. 2) PWR and CTL MMRs are merged to together. 3) ROD and PD_DAT3 bit masks are obsolete. 4) New RSI block size MMR is defined. 5) The definition of DMA descriptor set size is changed. 6) set_ios should powers up controller in 2 steps. In addition, this patch cleans up the spin locks. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Sonic Zhang
Chris Ball
Родитель
0462566b1e
Коммит
4ffdcf0469
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@ -24,9 +24,7 @@
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#include <asm/portmux.h>
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#include <asm/bfin_sdh.h>
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#if defined(CONFIG_BF51x)
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#define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
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#define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
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#if defined(CONFIG_BF51x) || defined(__ADSPBF60x__)
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#define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
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#define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
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#define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
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@ -45,8 +43,16 @@
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#define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
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#define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
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#define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
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#define bfin_write_SDH_E_MASK bfin_write_RSI_E_MASK
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#define bfin_read_SDH_CFG bfin_read_RSI_CFG
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#define bfin_write_SDH_CFG bfin_write_RSI_CFG
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# if defined(__ADSPBF60x__)
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# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
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# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
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# else
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# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
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# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
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# endif
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#endif
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struct sdh_host {
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@ -62,6 +68,7 @@ struct sdh_host {
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dma_addr_t sg_dma;
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int dma_len;
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unsigned long sclk;
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unsigned int imask;
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unsigned int power_mode;
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unsigned int clk_div;
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@ -127,11 +134,15 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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/* Only supports power-of-2 block size */
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if (data->blksz & (data->blksz - 1))
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return -EINVAL;
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#ifndef RSI_BLKSZ
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data_ctl |= ((ffs(data->blksz) - 1) << 4);
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#else
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bfin_write_SDH_BLK_SIZE(data->blksz);
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#endif
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bfin_write_SDH_DATA_CTL(data_ctl);
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/* the time of a host clock period in ns */
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cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
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cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
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timeout = data->timeout_ns / cycle_ns;
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timeout += data->timeout_clks;
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bfin_write_SDH_DATA_TIMER(timeout);
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@ -145,8 +156,13 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
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host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
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#if defined(CONFIG_BF54x)
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dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
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dma_cfg |= DMAFLOW_ARRAY | RESTART | WDSIZE_32 | DMAEN;
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# ifdef RSI_BLKSZ
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dma_cfg |= PSIZE_32 | NDSIZE_3;
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# else
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dma_cfg |= NDSIZE_5;
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# endif
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{
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struct scatterlist *sg;
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int i;
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@ -156,7 +172,7 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
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host->sg_cpu[i].x_modify = 4;
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dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
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"cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
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"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
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i, host->sg_cpu[i].start_addr,
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host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
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host->sg_cpu[i].x_modify);
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@ -172,6 +188,7 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
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set_dma_x_count(host->dma_ch, 0);
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set_dma_x_modify(host->dma_ch, 0);
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SSYNC();
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set_dma_config(host->dma_ch, dma_cfg);
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#elif defined(CONFIG_BF51x)
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/* RSI DMA doesn't work in array mode */
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@ -179,6 +196,7 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
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set_dma_x_count(host->dma_ch, length / 4);
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set_dma_x_modify(host->dma_ch, 4);
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SSYNC();
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set_dma_config(host->dma_ch, dma_cfg);
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#endif
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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@ -296,7 +314,6 @@ static int sdh_data_done(struct sdh_host *host, unsigned int stat)
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else
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data->bytes_xfered = 0;
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sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
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bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
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DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
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bfin_write_SDH_DATA_CTL(0);
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@ -321,74 +338,115 @@ static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
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dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
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WARN_ON(host->mrq != NULL);
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spin_lock(&host->lock);
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host->mrq = mrq;
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host->data = mrq->data;
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if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
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ret = sdh_setup_data(host, mrq->data);
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if (ret)
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return;
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goto data_err;
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}
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sdh_start_cmd(host, mrq->cmd);
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data_err:
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spin_unlock(&host->lock);
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}
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static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct sdh_host *host;
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unsigned long flags;
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u16 clk_ctl = 0;
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#ifndef RSI_BLKSZ
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u16 pwr_ctl = 0;
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#endif
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u16 cfg;
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host = mmc_priv(mmc);
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spin_lock_irqsave(&host->lock, flags);
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if (ios->clock) {
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unsigned long sys_clk, ios_clk;
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spin_lock(&host->lock);
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cfg = bfin_read_SDH_CFG();
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cfg |= MWE;
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switch (ios->bus_width) {
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case MMC_BUS_WIDTH_4:
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#ifndef RSI_BLKSZ
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cfg &= ~PD_SDDAT3;
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#endif
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cfg |= PUP_SDDAT3;
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/* Enable 4 bit SDIO */
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cfg |= SD4E;
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clk_ctl |= WIDE_BUS_4;
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break;
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case MMC_BUS_WIDTH_8:
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#ifndef RSI_BLKSZ
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cfg &= ~PD_SDDAT3;
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#endif
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cfg |= PUP_SDDAT3;
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/* Disable 4 bit SDIO */
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cfg &= ~SD4E;
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clk_ctl |= BYTE_BUS_8;
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break;
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default:
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cfg &= ~PUP_SDDAT3;
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/* Disable 4 bit SDIO */
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cfg &= ~SD4E;
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}
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host->power_mode = ios->power_mode;
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#ifndef RSI_BLKSZ
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
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pwr_ctl |= ROD_CTL;
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# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
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pwr_ctl |= SD_CMD_OD;
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# endif
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}
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if (ios->power_mode != MMC_POWER_OFF)
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pwr_ctl |= PWR_ON;
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else
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pwr_ctl &= ~PWR_ON;
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bfin_write_SDH_PWR_CTL(pwr_ctl);
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#else
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# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
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cfg |= SD_CMD_OD;
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else
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cfg &= ~SD_CMD_OD;
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# endif
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if (ios->power_mode != MMC_POWER_OFF)
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cfg |= PWR_ON;
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else
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cfg &= ~PWR_ON;
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bfin_write_SDH_CFG(cfg);
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#endif
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SSYNC();
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if (ios->power_mode == MMC_POWER_ON && ios->clock) {
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unsigned char clk_div;
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ios_clk = 2 * ios->clock;
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sys_clk = get_sclk();
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clk_div = sys_clk / ios_clk;
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if (sys_clk % ios_clk == 0)
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clk_div -= 1;
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clk_div = (get_sclk() / ios->clock - 1) / 2;
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clk_div = min_t(unsigned char, clk_div, 0xFF);
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clk_ctl |= clk_div;
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clk_ctl |= CLK_E;
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host->clk_div = clk_div;
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bfin_write_SDH_CLK_CTL(clk_ctl);
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} else
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sdh_stop_clock(host);
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
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#ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
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pwr_ctl |= ROD_CTL;
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#else
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pwr_ctl |= SD_CMD_OD | ROD_CTL;
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#endif
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if (ios->bus_width == MMC_BUS_WIDTH_4) {
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cfg = bfin_read_SDH_CFG();
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cfg &= ~PD_SDDAT3;
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cfg |= PUP_SDDAT3;
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/* Enable 4 bit SDIO */
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cfg |= (SD4E | MWE);
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bfin_write_SDH_CFG(cfg);
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clk_ctl |= WIDE_BUS;
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} else {
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cfg = bfin_read_SDH_CFG();
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cfg |= MWE;
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bfin_write_SDH_CFG(cfg);
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}
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bfin_write_SDH_CLK_CTL(clk_ctl);
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host->power_mode = ios->power_mode;
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/* set up sdh interrupt mask*/
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if (ios->power_mode == MMC_POWER_ON)
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pwr_ctl |= PWR_ON;
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bfin_write_SDH_PWR_CTL(pwr_ctl);
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bfin_write_SDH_MASK0(DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
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RX_OVERRUN | TX_UNDERRUN | CMD_SENT | CMD_RESP_END |
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CMD_TIME_OUT | CMD_CRC_FAIL);
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else
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bfin_write_SDH_MASK0(0);
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SSYNC();
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spin_unlock_irqrestore(&host->lock, flags);
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spin_unlock(&host->lock);
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dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
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host->clk_div,
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@ -405,7 +463,7 @@ static irqreturn_t sdh_dma_irq(int irq, void *devid)
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{
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struct sdh_host *host = devid;
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dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
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dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
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get_dma_curr_irqstat(host->dma_ch));
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clear_dma_irqstat(host->dma_ch);
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SSYNC();
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@ -420,6 +478,9 @@ static irqreturn_t sdh_stat_irq(int irq, void *devid)
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int handled = 0;
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dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
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spin_lock(&host->lock);
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status = bfin_read_SDH_E_STATUS();
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if (status & SD_CARD_DET) {
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mmc_detect_change(host->mmc, 0);
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@ -437,6 +498,8 @@ static irqreturn_t sdh_stat_irq(int irq, void *devid)
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if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
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handled |= sdh_data_done(host, status);
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spin_unlock(&host->lock);
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dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
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return IRQ_RETVAL(handled);
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@ -462,12 +525,16 @@ static int __devinit sdh_probe(struct platform_device *pdev)
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}
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mmc->ops = &sdh_ops;
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#if defined(CONFIG_BF54x)
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mmc->max_segs = 32;
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#elif defined(CONFIG_BF51x)
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#if defined(CONFIG_BF51x)
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mmc->max_segs = 1;
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#else
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mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
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#endif
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#ifdef RSI_BLKSZ
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mmc->max_seg_size = -1;
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#else
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mmc->max_seg_size = 1 << 16;
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#endif
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mmc->max_blk_size = 1 << 11;
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mmc->max_blk_count = 1 << 11;
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mmc->max_req_size = PAGE_SIZE;
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@ -477,6 +544,7 @@ static int __devinit sdh_probe(struct platform_device *pdev)
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mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
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host = mmc_priv(mmc);
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host->mmc = mmc;
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host->sclk = get_sclk();
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spin_lock_init(&host->lock);
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host->irq = drv_data->irq_int0;
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@ -501,7 +569,6 @@ static int __devinit sdh_probe(struct platform_device *pdev)
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}
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platform_set_drvdata(pdev, mmc);
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mmc_add_host(mmc);
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ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
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if (ret) {
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@ -522,12 +589,13 @@ static int __devinit sdh_probe(struct platform_device *pdev)
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
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SSYNC();
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/* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
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/* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
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* mmc stack will do the detection.
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*/
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bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
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SSYNC();
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mmc_add_host(mmc);
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return 0;
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out4:
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@ -575,7 +643,11 @@ static int sdh_suspend(struct platform_device *dev, pm_message_t state)
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if (mmc)
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ret = mmc_suspend_host(mmc);
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#ifndef RSI_BLKSZ
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bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
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#else
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() & ~PWR_ON);
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#endif
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peripheral_free_list(drv_data->pin_req);
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return ret;
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@ -593,12 +665,16 @@ static int sdh_resume(struct platform_device *dev)
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return ret;
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}
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bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
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#if defined(CONFIG_BF54x)
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/* Secure Digital Host shares DMA with Nand controller */
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bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
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#endif
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#ifndef RSI_BLKSZ
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bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
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#else
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN | PWR_ON);
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#endif
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SSYNC();
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bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
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