drm/i915 fixes for v5.0-rc7:
- combo phy programming fix - opregion version check fix for VBT RVDA lookup - gem mmap ioctl race fix - fbdev hpd during suspend fix - array size bounds check fix in pmu -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEFWWmW3ewYy4RJOWc05gHnSar7m8FAlxkELIACgkQ05gHnSar 7m+4tA//W7PitAnfeSqnQN19dBkJ2kmxwfmoCFRRBne1998EOcx8PIoFtodi1ySF N2vy40gACINAcUssBqcXalBPQYmRhSvQzzMLl+y8jF7K1Xb4SnlGnKjkf2SbMSBM X/R1p3gTpjxRGE5KReUZtvuaSeJAvLm3Cc/Llj7Q5FoPUBTgTxg6ejjwN1SkvM4Y Hx8hX6cevNmk0+RRaet08nVTpG/3zHzqAp0mQs7HtJNDAxJWoF9FE9u9MkZbOI1g 4ZPtecWB3gKu2lYVTCZ3HNZvsW42ZwgwfKWos8RwkG2Hp9L7Dq5xiNUcWA3fpK+1 /DNj/taQx3a9fOqbakhuWB7refPRn2TMos+fKz0fnYK2nYNLLC7MMRQDO/dcLLTZ 44Grdo7vx8sF7ZvNVV8tPTPvDeKQ6YiqPM+RMgY2fiNjxkIhAWR+UoXhZNfw1sT9 3ECy6rGj2GZT8HfjKzkS7y/Ni8ReaQ79kkpMSqWMMNxhpjVwn/mYNplkXgTM1wD0 HX/AYQTzbjI0mJc2YSyrI0r+lcaxz9NG4HuCo54ZFfTmTDpkeX+cWubjeE/i8Dh7 g0P4nvzC2baQ9AWHEr3WGr6/8w00y2TIv7eyWIOi4IB5qRgv5vv5v4CPpbLGkB1l vrSqzpabIOtLLCIP78QFHQk+GvZxFiOtiohb3yIUIl0e4RDKH/Y= =i2Rn -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2019-02-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.0-rc7: - combo phy programming fix - opregion version check fix for VBT RVDA lookup - gem mmap ioctl race fix - fbdev hpd during suspend fix - array size bounds check fix in pmu Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/877ee3504b.fsf@intel.com
This commit is contained in:
Dave Airlie
Коммит
5016bd2480
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@ -1824,6 +1824,16 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
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return 0;
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}
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static inline bool
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__vma_matches(struct vm_area_struct *vma, struct file *filp,
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unsigned long addr, unsigned long size)
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{
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if (vma->vm_file != filp)
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return false;
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return vma->vm_start == addr && (vma->vm_end - vma->vm_start) == size;
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}
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/**
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* i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
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* it is mapped to.
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@ -1882,7 +1892,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
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return -EINTR;
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}
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vma = find_vma(mm, addr);
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if (vma)
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if (vma && __vma_matches(vma, obj->base.filp, addr, args->size))
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vma->vm_page_prot =
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pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
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else
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@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event)
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* Update the bitmask of enabled events and increment
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* the event reference counter.
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*/
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GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
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BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
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GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
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GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
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i915->pmu.enable |= BIT_ULL(bit);
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i915->pmu.enable_count[bit]++;
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@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event)
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engine = intel_engine_lookup_user(i915,
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engine_event_class(event),
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engine_event_instance(event));
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GEM_BUG_ON(!engine);
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engine->pmu.enable |= BIT(sample);
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GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
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BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
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I915_ENGINE_SAMPLE_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
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I915_ENGINE_SAMPLE_COUNT);
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GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
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GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
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GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
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engine->pmu.enable |= BIT(sample);
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engine->pmu.enable_count[sample]++;
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}
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@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event)
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engine = intel_engine_lookup_user(i915,
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engine_event_class(event),
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engine_event_instance(event));
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GEM_BUG_ON(!engine);
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GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
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GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
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GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
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GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
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/*
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* Decrement the reference count and clear the enabled
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* bitmask when the last listener on an event goes away.
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@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event)
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engine->pmu.enable &= ~BIT(sample);
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}
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GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
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GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
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GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
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/*
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* Decrement the reference count and clear the enabled
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@ -31,6 +31,8 @@ enum {
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((1 << I915_PMU_SAMPLE_BITS) + \
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(I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
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#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
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struct i915_pmu_sample {
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u64 cur;
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};
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@ -1790,7 +1790,7 @@ enum i915_power_well_id {
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#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
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#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
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#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
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#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
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#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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@ -1798,7 +1798,7 @@ enum i915_power_well_id {
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_F_GRP_OFFSET) + \
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4 * (dw))
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#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
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#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
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_CNL_PORT_TX_AE_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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@ -1834,9 +1834,9 @@ enum i915_power_well_id {
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#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
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#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
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#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
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#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
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((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
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_CNL_PORT_TX_DW4_LN0_AE)))
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#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
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@ -1864,8 +1864,12 @@ enum i915_power_well_id {
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#define RTERM_SELECT(x) ((x) << 3)
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#define RTERM_SELECT_MASK (0x7 << 3)
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
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#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
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#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
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#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
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#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
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#define N_SCALAR(x) ((x) << 24)
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#define N_SCALAR_MASK (0x7F << 24)
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@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
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{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
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};
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struct icl_combo_phy_ddi_buf_trans {
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u32 dw2_swing_select;
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u32 dw2_swing_scalar;
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u32 dw4_scaling;
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/* icl_combo_phy_ddi_translations */
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static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
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/* NT mV Trans mV db */
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{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
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{ 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
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{ 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
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{ 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
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{ 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
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{ 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
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{ 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
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{ 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
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{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
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{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
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};
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/* Voltage Swing Programming for VccIO 0.85V for DP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
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/* Voltage mV db */
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{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
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{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
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{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
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{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
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{ 0xB, 0x70, 0x0018 }, /* 600 0.0 */
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{ 0xB, 0x70, 0x3015 }, /* 600 3.5 */
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{ 0xB, 0x70, 0x6012 }, /* 600 6.0 */
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{ 0x5, 0x00, 0x0018 }, /* 800 0.0 */
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{ 0x5, 0x00, 0x3015 }, /* 800 3.5 */
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{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
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static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
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/* NT mV Trans mV db */
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{ 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
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{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
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{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
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{ 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
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{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
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{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
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{ 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
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{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
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{ 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
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{ 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
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};
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/* FIXME - After table is updated in Bspec */
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/* Voltage Swing Programming for VccIO 0.85V for eDP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
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/* Voltage mV db */
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{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
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{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
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static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
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/* NT mV Trans mV db */
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{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
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{ 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
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{ 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
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{ 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
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{ 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
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{ 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
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{ 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
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{ 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
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{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
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{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
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};
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/* Voltage Swing Programming for VccIO 0.95V for DP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
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/* Voltage mV db */
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{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
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{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
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{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
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{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
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{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */
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{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */
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{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */
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{ 0x5, 0x76, 0x0018 }, /* 800 0.0 */
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{ 0x5, 0x76, 0x3015 }, /* 800 3.5 */
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{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
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};
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/* FIXME - After table is updated in Bspec */
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/* Voltage Swing Programming for VccIO 0.95V for eDP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
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/* Voltage mV db */
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{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
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{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
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};
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/* Voltage Swing Programming for VccIO 1.05V for DP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
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/* Voltage mV db */
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{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
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{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
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{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
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{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
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{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */
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{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */
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{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */
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{ 0x5, 0x71, 0x0018 }, /* 800 0.0 */
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{ 0x5, 0x71, 0x3015 }, /* 800 3.5 */
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{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
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};
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/* FIXME - After table is updated in Bspec */
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/* Voltage Swing Programming for VccIO 1.05V for eDP */
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static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
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/* Voltage mV db */
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{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
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{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
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{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
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{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
|
||||
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
|
||||
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
|
||||
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
|
||||
static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
|
||||
{ 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
|
||||
{ 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
|
||||
{ 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
|
||||
{ 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
|
||||
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
|
||||
{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
|
||||
};
|
||||
|
||||
struct icl_mg_phy_ddi_buf_trans {
|
||||
|
|
@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
|
|||
}
|
||||
}
|
||||
|
||||
static const struct icl_combo_phy_ddi_buf_trans *
|
||||
static const struct cnl_ddi_buf_trans *
|
||||
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
|
||||
int type, int *n_entries)
|
||||
int type, int rate, int *n_entries)
|
||||
{
|
||||
u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
|
||||
|
||||
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
|
||||
switch (voltage) {
|
||||
case VOLTAGE_INFO_0_85V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
|
||||
return icl_combo_phy_ddi_translations_edp_0_85V;
|
||||
case VOLTAGE_INFO_0_95V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
|
||||
return icl_combo_phy_ddi_translations_edp_0_95V;
|
||||
case VOLTAGE_INFO_1_05V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
|
||||
return icl_combo_phy_ddi_translations_edp_1_05V;
|
||||
default:
|
||||
MISSING_CASE(voltage);
|
||||
return NULL;
|
||||
}
|
||||
} else {
|
||||
switch (voltage) {
|
||||
case VOLTAGE_INFO_0_85V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
|
||||
return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
|
||||
case VOLTAGE_INFO_0_95V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
|
||||
return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
|
||||
case VOLTAGE_INFO_1_05V:
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
|
||||
return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
|
||||
default:
|
||||
MISSING_CASE(voltage);
|
||||
return NULL;
|
||||
}
|
||||
if (type == INTEL_OUTPUT_HDMI) {
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
|
||||
return icl_combo_phy_ddi_translations_hdmi;
|
||||
} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
|
||||
return icl_combo_phy_ddi_translations_edp_hbr3;
|
||||
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
|
||||
return icl_combo_phy_ddi_translations_edp_hbr2;
|
||||
}
|
||||
|
||||
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
|
||||
return icl_combo_phy_ddi_translations_dp_hbr2;
|
||||
}
|
||||
|
||||
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
|
||||
|
|
@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
|
|||
|
||||
if (IS_ICELAKE(dev_priv)) {
|
||||
if (intel_port_is_combophy(dev_priv, port))
|
||||
icl_get_combo_buf_trans(dev_priv, port,
|
||||
INTEL_OUTPUT_HDMI, &n_entries);
|
||||
icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
|
||||
0, &n_entries);
|
||||
else
|
||||
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
|
||||
default_entry = n_entries - 1;
|
||||
|
|
@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
|
|||
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||
enum port port = encoder->port;
|
||||
int n_entries;
|
||||
|
||||
if (IS_ICELAKE(dev_priv)) {
|
||||
if (intel_port_is_combophy(dev_priv, port))
|
||||
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
|
||||
&n_entries);
|
||||
intel_dp->link_rate, &n_entries);
|
||||
else
|
||||
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
|
|
@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
|
|||
}
|
||||
|
||||
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
|
||||
u32 level, enum port port, int type)
|
||||
u32 level, enum port port, int type,
|
||||
int rate)
|
||||
{
|
||||
const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
|
||||
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
|
||||
u32 n_entries, val;
|
||||
int ln;
|
||||
|
||||
ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
|
||||
&n_entries);
|
||||
rate, &n_entries);
|
||||
if (!ddi_translations)
|
||||
return;
|
||||
|
||||
|
|
@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
|
|||
level = n_entries - 1;
|
||||
}
|
||||
|
||||
/* Set PORT_TX_DW5 Rterm Sel to 110b. */
|
||||
/* Set PORT_TX_DW5 */
|
||||
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
|
||||
val &= ~RTERM_SELECT_MASK;
|
||||
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
|
||||
TAP2_DISABLE | TAP3_DISABLE);
|
||||
val |= SCALING_MODE_SEL(0x2);
|
||||
val |= RTERM_SELECT(0x6);
|
||||
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW5 */
|
||||
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
|
||||
/* Set DisableTap2 and DisableTap3 if MIPI DSI
|
||||
* Clear DisableTap2 and DisableTap3 for all other Ports
|
||||
*/
|
||||
if (type == INTEL_OUTPUT_DSI) {
|
||||
val |= TAP2_DISABLE;
|
||||
val |= TAP3_DISABLE;
|
||||
} else {
|
||||
val &= ~TAP2_DISABLE;
|
||||
val &= ~TAP3_DISABLE;
|
||||
}
|
||||
val |= TAP3_DISABLE;
|
||||
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW2 */
|
||||
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
|
||||
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
|
||||
RCOMP_SCALAR_MASK);
|
||||
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
|
||||
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
|
||||
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
|
||||
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
|
||||
/* Program Rcomp scalar for every table entry */
|
||||
val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
|
||||
val |= RCOMP_SCALAR(0x98);
|
||||
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW4 */
|
||||
|
|
@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
|
|||
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
|
||||
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
|
||||
CURSOR_COEFF_MASK);
|
||||
val |= ddi_translations[level].dw4_scaling;
|
||||
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
|
||||
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
|
||||
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
|
||||
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
|
||||
}
|
||||
|
||||
/* Program PORT_TX_DW7 */
|
||||
val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
|
||||
val &= ~N_SCALAR_MASK;
|
||||
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
|
||||
I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
|
||||
}
|
||||
|
||||
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
||||
|
|
@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
|||
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* 5. Program swing and de-emphasis */
|
||||
icl_ddi_combo_vswing_program(dev_priv, level, port, type);
|
||||
icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
|
||||
|
||||
/* 6. Set training enable to trigger update */
|
||||
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
|
||||
|
|
|
|||
|
|
@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
|
|||
static int icl_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
enum port port = dig_port->base.port;
|
||||
|
||||
if (port == PORT_B)
|
||||
if (intel_port_is_combophy(dev_priv, port) &&
|
||||
!intel_dp_is_edp(intel_dp))
|
||||
return 540000;
|
||||
|
||||
return 810000;
|
||||
|
|
|
|||
|
|
@ -209,6 +209,16 @@ struct intel_fbdev {
|
|||
unsigned long vma_flags;
|
||||
async_cookie_t cookie;
|
||||
int preferred_bpp;
|
||||
|
||||
/* Whether or not fbdev hpd processing is temporarily suspended */
|
||||
bool hpd_suspended : 1;
|
||||
/* Set when a hotplug was received while HPD processing was
|
||||
* suspended
|
||||
*/
|
||||
bool hpd_waiting : 1;
|
||||
|
||||
/* Protects hpd_suspended */
|
||||
struct mutex hpd_lock;
|
||||
};
|
||||
|
||||
struct intel_encoder {
|
||||
|
|
|
|||
|
|
@ -679,6 +679,7 @@ int intel_fbdev_init(struct drm_device *dev)
|
|||
if (ifbdev == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&ifbdev->hpd_lock);
|
||||
drm_fb_helper_prepare(dev, &ifbdev->helper, &intel_fb_helper_funcs);
|
||||
|
||||
if (!intel_fbdev_init_bios(dev, ifbdev))
|
||||
|
|
@ -752,6 +753,26 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
|
|||
intel_fbdev_destroy(ifbdev);
|
||||
}
|
||||
|
||||
/* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD
|
||||
* processing, fbdev will perform a full connector reprobe if a hotplug event
|
||||
* was received while HPD was suspended.
|
||||
*/
|
||||
static void intel_fbdev_hpd_set_suspend(struct intel_fbdev *ifbdev, int state)
|
||||
{
|
||||
bool send_hpd = false;
|
||||
|
||||
mutex_lock(&ifbdev->hpd_lock);
|
||||
ifbdev->hpd_suspended = state == FBINFO_STATE_SUSPENDED;
|
||||
send_hpd = !ifbdev->hpd_suspended && ifbdev->hpd_waiting;
|
||||
ifbdev->hpd_waiting = false;
|
||||
mutex_unlock(&ifbdev->hpd_lock);
|
||||
|
||||
if (send_hpd) {
|
||||
DRM_DEBUG_KMS("Handling delayed fbcon HPD event\n");
|
||||
drm_fb_helper_hotplug_event(&ifbdev->helper);
|
||||
}
|
||||
}
|
||||
|
||||
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
|
@ -773,6 +794,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
|||
*/
|
||||
if (state != FBINFO_STATE_RUNNING)
|
||||
flush_work(&dev_priv->fbdev_suspend_work);
|
||||
|
||||
console_lock();
|
||||
} else {
|
||||
/*
|
||||
|
|
@ -800,17 +822,26 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
|||
|
||||
drm_fb_helper_set_suspend(&ifbdev->helper, state);
|
||||
console_unlock();
|
||||
|
||||
intel_fbdev_hpd_set_suspend(ifbdev, state);
|
||||
}
|
||||
|
||||
void intel_fbdev_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
|
||||
bool send_hpd;
|
||||
|
||||
if (!ifbdev)
|
||||
return;
|
||||
|
||||
intel_fbdev_sync(ifbdev);
|
||||
if (ifbdev->vma || ifbdev->helper.deferred_setup)
|
||||
|
||||
mutex_lock(&ifbdev->hpd_lock);
|
||||
send_hpd = !ifbdev->hpd_suspended;
|
||||
ifbdev->hpd_waiting = true;
|
||||
mutex_unlock(&ifbdev->hpd_lock);
|
||||
|
||||
if (send_hpd && (ifbdev->vma || ifbdev->helper.deferred_setup))
|
||||
drm_fb_helper_hotplug_event(&ifbdev->helper);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,12 @@
|
|||
struct opregion_header {
|
||||
u8 signature[16];
|
||||
u32 size;
|
||||
u32 opregion_ver;
|
||||
struct {
|
||||
u8 rsvd;
|
||||
u8 revision;
|
||||
u8 minor;
|
||||
u8 major;
|
||||
} __packed over;
|
||||
u8 bios_ver[32];
|
||||
u8 vbios_ver[16];
|
||||
u8 driver_ver[16];
|
||||
|
|
@ -119,7 +124,8 @@ struct opregion_asle {
|
|||
u64 fdss;
|
||||
u32 fdsp;
|
||||
u32 stat;
|
||||
u64 rvda; /* Physical address of raw vbt data */
|
||||
u64 rvda; /* Physical (2.0) or relative from opregion (2.1+)
|
||||
* address of raw VBT data. */
|
||||
u32 rvds; /* Size of raw vbt data */
|
||||
u8 rsvd[58];
|
||||
} __packed;
|
||||
|
|
@ -925,6 +931,11 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
|
|||
opregion->header = base;
|
||||
opregion->lid_state = base + ACPI_CLID;
|
||||
|
||||
DRM_DEBUG_DRIVER("ACPI OpRegion version %u.%u.%u\n",
|
||||
opregion->header->over.major,
|
||||
opregion->header->over.minor,
|
||||
opregion->header->over.revision);
|
||||
|
||||
mboxes = opregion->header->mboxes;
|
||||
if (mboxes & MBOX_ACPI) {
|
||||
DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
|
||||
|
|
@ -953,11 +964,26 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
|
|||
if (dmi_check_system(intel_no_opregion_vbt))
|
||||
goto out;
|
||||
|
||||
if (opregion->header->opregion_ver >= 2 && opregion->asle &&
|
||||
if (opregion->header->over.major >= 2 && opregion->asle &&
|
||||
opregion->asle->rvda && opregion->asle->rvds) {
|
||||
opregion->rvda = memremap(opregion->asle->rvda,
|
||||
opregion->asle->rvds,
|
||||
resource_size_t rvda = opregion->asle->rvda;
|
||||
|
||||
/*
|
||||
* opregion 2.0: rvda is the physical VBT address.
|
||||
*
|
||||
* opregion 2.1+: rvda is unsigned, relative offset from
|
||||
* opregion base, and should never point within opregion.
|
||||
*/
|
||||
if (opregion->header->over.major > 2 ||
|
||||
opregion->header->over.minor >= 1) {
|
||||
WARN_ON(rvda < OPREGION_SIZE);
|
||||
|
||||
rvda += asls;
|
||||
}
|
||||
|
||||
opregion->rvda = memremap(rvda, opregion->asle->rvds,
|
||||
MEMREMAP_WB);
|
||||
|
||||
vbt = opregion->rvda;
|
||||
vbt_size = opregion->asle->rvds;
|
||||
if (intel_bios_is_valid_vbt(vbt, vbt_size)) {
|
||||
|
|
@ -967,6 +993,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
|
|||
goto out;
|
||||
} else {
|
||||
DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n");
|
||||
memunmap(opregion->rvda);
|
||||
opregion->rvda = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -415,16 +415,17 @@ struct intel_engine_cs {
|
|||
/**
|
||||
* @enable_count: Reference count for the enabled samplers.
|
||||
*
|
||||
* Index number corresponds to the bit number from @enable.
|
||||
* Index number corresponds to @enum drm_i915_pmu_engine_sample.
|
||||
*/
|
||||
unsigned int enable_count[I915_PMU_SAMPLE_BITS];
|
||||
unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
|
||||
/**
|
||||
* @sample: Counter values for sampling events.
|
||||
*
|
||||
* Our internal timer stores the current counters in this field.
|
||||
*
|
||||
* Index number corresponds to @enum drm_i915_pmu_engine_sample.
|
||||
*/
|
||||
#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
|
||||
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
|
||||
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
|
||||
} pmu;
|
||||
|
||||
/*
|
||||
|
|
|
|||
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