ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth values
pt_regs->event was set with artificial values to identify the low level
system event (syscall trap / breakpoint trap / exceptions / interrupts)
With r8 saving out of the way, the full word can be used to save real
ECR (Exception Cause Register) which helps idenify the event naturally,
including additional info such as cause code, param.
Only for Interrupts, where ECR is not applicable, do we resort to
synthetic non ECR values.
SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with
different runtime values.
The ptrace helpers now use the sub-fields of ECR to distinguish the
events (e.g. vector 0x25 is trap, param 0 is syscall...)
The following benefits will follow:
(1) This centralizes the location of where ECR is saved and will allow
the cleanup of task->thread.cause_code ECR placeholder which is set
in non-uniform way. Then ARC VM code can safely rely on it being
there for purpose of finer grained VM_EXEC dcache flush (based on
exec fault: I-TLB Miss)
(2) Further, ECR being passed around from low level handlers as arg can
be eliminated as it is part of standard reg-file in pt_regs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
Родитель
352c1d95e3
Коммит
502a0c775c
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@ -60,6 +60,7 @@
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#define ECR_V_ITLB_MISS 0x21
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#define ECR_V_DTLB_MISS 0x22
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#define ECR_V_PROTV 0x23
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#define ECR_V_TRAP 0x25
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/* Protection Violation Exception Cause Code Values */
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#define ECR_C_PROTV_INST_FETCH 0x00
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@ -77,6 +78,9 @@
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#define ECR_C_BIT_DTLB_LD_MISS 8
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#define ECR_C_BIT_DTLB_ST_MISS 9
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/* Dummy ECR values for Interrupts */
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#define event_IRQ1 0x0031abcd
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#define event_IRQ2 0x0032abcd
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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@ -309,7 +309,7 @@
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#endif
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/* Save Pre Intr/Exception User SP on kernel stack */
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st.a sp, [r9, -16] ; Make room for orig_r0, orig_r8, user_r25
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st.a sp, [r9, -16] ; Make room for orig_r0, ECR, user_r25
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/* CAUTION:
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* SP should be set at the very end when we are done with everything
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@ -391,9 +391,10 @@
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* Note that syscalls are implemented via TRAP which is also a exception
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* from CPU's point of view
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_EXCEPTION marker
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.macro SAVE_ALL_SYS
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st \marker, [sp, 8] /* orig_r8 */
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lr r9, [ecr]
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st r9, [sp, 8] /* ECR */
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st r0, [sp, 4] /* orig_r0, needed only for sys calls */
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/* Restore r9 used to code the early prologue */
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@ -411,20 +412,6 @@
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PUSHAX erbta
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.endm
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/*--------------------------------------------------------------
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* Save scratch regs for exceptions
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_SYS
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SAVE_ALL_EXCEPTION orig_r8_IS_EXCPN
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.endm
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/*--------------------------------------------------------------
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* Save scratch regs for sys calls
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_TRAP
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SAVE_ALL_EXCEPTION orig_r8_IS_SCALL
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by system call or Exceptions
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* SP should always be pointing to the next free stack element
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@ -452,7 +439,7 @@
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RESTORE_R12_TO_R0
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ld sp, [sp] /* restore original sp */
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/* orig_r0, orig_r8, user_r25 skipped automatically */
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/* orig_r0, ECR, user_r25 skipped automatically */
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.endm
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@ -469,7 +456,7 @@
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#endif
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/* now we are ready to save the remaining context :) */
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st orig_r8_IS_IRQ1, [sp, 8] /* Event Type */
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st event_IRQ1, [sp, 8] /* Dummy ECR */
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st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
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SAVE_R0_TO_R12
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@ -494,7 +481,7 @@
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ld r9, [@int2_saved_reg]
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/* now we are ready to save the remaining context :) */
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st orig_r8_IS_IRQ2, [sp, 8] /* Event Type */
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st event_IRQ2, [sp, 8] /* Dummy ECR */
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st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
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SAVE_R0_TO_R12
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@ -535,7 +522,7 @@
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RESTORE_R12_TO_R0
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ld sp, [sp] /* restore original sp */
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/* orig_r0, orig_r8, user_r25 skipped automatically */
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/* orig_r0, ECR, user_r25 skipped automatically */
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.endm
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.macro RESTORE_ALL_INT2
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@ -554,7 +541,7 @@
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RESTORE_R12_TO_R0
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ld sp, [sp] /* restore original sp */
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/* orig_r0, orig_r8, user_r25 skipped automatically */
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/* orig_r0, ECR, user_r25 skipped automatically */
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.endm
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@ -44,15 +44,24 @@ struct pt_regs {
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long sp; /* user/kernel sp depending on where we came from */
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long orig_r0;
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/*to distinguish bet excp, syscall, irq */
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/*
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* To distinguish bet excp, syscall, irq
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* For traps and exceptions, Exception Cause Register.
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* ECR: <00> <VV> <CC> <PP>
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* Last word used by Linux for extra state mgmt (syscall-restart)
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* For interrupts, use artificial ECR values to note current prio-level
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*/
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union {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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/* so that assembly code is same for LE/BE */
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unsigned long orig_r8:16, event:16;
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unsigned long state:8, ecr_vec:8,
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ecr_cause:8, ecr_param:8;
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#else
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unsigned long event:16, orig_r8:16;
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unsigned long ecr_param:8, ecr_cause:8,
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ecr_vec:8, state:8;
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#endif
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long orig_r8_word;
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};
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unsigned long event;
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};
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long user_r25;
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@ -94,11 +103,13 @@ struct callee_regs {
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/* return 1 if PC in delay slot */
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#define delay_mode(regs) ((regs->status32 & STATUS_DE_MASK) == STATUS_DE_MASK)
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#define in_syscall(regs) (regs->event & orig_r8_IS_SCALL)
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#define in_brkpt_trap(regs) (regs->event & orig_r8_IS_BRKPT)
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#define in_syscall(regs) ((regs->ecr_vec == ECR_V_TRAP) && !regs->ecr_param)
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#define in_brkpt_trap(regs) ((regs->ecr_vec == ECR_V_TRAP) && regs->ecr_param)
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#define syscall_wont_restart(regs) (regs->event |= orig_r8_IS_SCALL_RESTARTED)
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#define syscall_restartable(regs) !(regs->event & orig_r8_IS_SCALL_RESTARTED)
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#define STATE_SCALL_RESTARTED 0x01
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#define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED)
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#define syscall_restartable(reg) !(reg->state & STATE_SCALL_RESTARTED)
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#define current_pt_regs() \
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({ \
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@ -115,11 +126,4 @@ static inline long regs_return_value(struct pt_regs *regs)
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#endif /* !__ASSEMBLY__ */
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#define orig_r8_IS_SCALL 0x0001
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#define orig_r8_IS_SCALL_RESTARTED 0x0002
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#define orig_r8_IS_BRKPT 0x0004
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#define orig_r8_IS_EXCPN 0x0008
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#define orig_r8_IS_IRQ1 0x0010
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#define orig_r8_IS_IRQ2 0x0020
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#endif /* __ASM_PTRACE_H */
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@ -46,7 +46,7 @@ int main(void)
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BLANK();
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DEFINE(PT_status32, offsetof(struct pt_regs, status32));
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DEFINE(PT_orig_r8, offsetof(struct pt_regs, orig_r8_word));
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DEFINE(PT_event, offsetof(struct pt_regs, event));
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DEFINE(PT_sp, offsetof(struct pt_regs, sp));
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DEFINE(PT_r0, offsetof(struct pt_regs, r0));
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DEFINE(PT_r1, offsetof(struct pt_regs, r1));
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@ -142,7 +142,7 @@ VECTOR reserved ; Reserved Exceptions
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.endr
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#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
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#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
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#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,SYS...} */
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#include <asm/errno.h>
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#include <asm/arcregs.h>
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#include <asm/irqflags.h>
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@ -495,8 +495,6 @@ tracesys_exit:
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trap_with_param:
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; stop_pc info by gdb needs this info
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stw orig_r8_IS_BRKPT, [sp, PT_orig_r8]
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mov r0, r12
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lr r1, [efa]
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mov r2, sp
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@ -541,7 +539,7 @@ ARC_ENTRY EV_Trap
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_TRAP
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SAVE_ALL_SYS
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;------- (4) What caused the Trap --------------
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lr r12, [ecr]
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@ -696,8 +694,17 @@ not_exception:
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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; Level 2 interrupt return Path - from hardware standpoint
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bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
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;------------------------------------------------------------------
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; However the context returning might not have taken L2 intr itself
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; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
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; Special considerations needed for the context which took L2 intr
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ld r9, [sp, PT_event] ; Ensure this is L2 intr context
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brne r9, event_IRQ2, 149f
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;------------------------------------------------------------------
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; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
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; so that sched doesnt move to new task, causing L1 to be delayed
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@ -705,19 +712,15 @@ not_exception:
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; things to what they were, before returning from L2 context
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;----------------------------------------------------------------
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ldw r9, [sp, PT_orig_r8] ; get orig_r8 to make sure it is
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brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path
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ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
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bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
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; A1 is set in status32_l2
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; decrement thread_info->preempt_count (re-enable preemption)
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GET_CURR_THR_INFO_FROM_SP r10
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ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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; paranoid check, given A1 was active when A2 happened, preempt count
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; must not be 0 beccause we would have incremented it.
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; must not be 0 because we would have incremented it.
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; If this does happen we simply HALT as it means a BUG !!!
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cmp r9, 0
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bnz 2f
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@ -181,7 +181,7 @@ void kgdb_trap(struct pt_regs *regs, int param)
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* with trap_s 4 (compiled) breakpoints, continuation needs to
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* start after the breakpoint.
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*/
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if (param == 3)
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if (regs->ecr_param == 3)
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instruction_pointer(regs) -= BREAK_INSTR_SIZE;
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kgdb_handle_exception(1, SIGTRAP, 0, regs);
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@ -76,7 +76,7 @@ asmlinkage void ret_from_fork(void);
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* ------------------
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* | SP |
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* | orig_r0 |
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* | orig_r8 |
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* | event/ECR |
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* | user_r25 |
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* ------------------ <===== END of PAGE
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*/
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@ -117,17 +117,16 @@ static void show_faulting_vma(unsigned long address, char *buf)
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static void show_ecr_verbose(struct pt_regs *regs)
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{
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unsigned int vec, cause_code, cause_reg;
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unsigned int vec, cause_code;
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unsigned long address;
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cause_reg = current->thread.cause_code;
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pr_info("\n[ECR ]: 0x%08x => ", cause_reg);
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pr_info("\n[ECR ]: 0x%08lx => ", regs->event);
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/* For Data fault, this is data address not instruction addr */
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address = current->thread.fault_address;
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vec = cause_reg >> 16;
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cause_code = (cause_reg >> 8) & 0xFF;
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vec = regs->ecr_vec;
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cause_code = regs->ecr_cause;
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/* For DTLB Miss or ProtV, display the memory involved too */
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if (vec == ECR_V_DTLB_MISS) {
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@ -174,8 +173,7 @@ void show_regs(struct pt_regs *regs)
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print_task_path_n_nm(tsk, buf);
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show_regs_print_info(KERN_INFO);
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if (current->thread.cause_code)
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show_ecr_verbose(regs);
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show_ecr_verbose(regs);
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pr_info("[EFA ]: 0x%08lx\n[BLINK ]: %pS\n[ERET ]: %pS\n",
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current->thread.fault_address,
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