mtd: rawnand: qcom: update last code word register
From QPIC v2 onwards a new register got added to read last code word.Add support for this READ_LOCATION_LAST_CW_n register. In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through READ_LOCATION_n, while codeword 3 will be accessed through READ_LOCATION_LAST_CW_n. Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1614109141-7531-5-git-send-email-mdalam@codeaurora.org
This commit is contained in:
Md Sadre Alam
Miquel Raynal
Родитель
e7a307f21a
Коммит
503ee5aad4
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@ -48,6 +48,10 @@
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#define NAND_READ_LOCATION_1 0xf24
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#define NAND_READ_LOCATION_2 0xf28
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#define NAND_READ_LOCATION_3 0xf2c
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#define NAND_READ_LOCATION_LAST_CW_0 0xf40
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#define NAND_READ_LOCATION_LAST_CW_1 0xf44
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#define NAND_READ_LOCATION_LAST_CW_2 0xf48
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#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
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/* dummy register offsets, used by write_reg_dma */
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#define NAND_DEV_CMD1_RESTORE 0xdead
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@ -187,6 +191,11 @@ nandc_set_reg(chip, reg, \
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((read_size) << READ_LOCATION_SIZE) | \
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((is_last_read_loc) << READ_LOCATION_LAST))
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#define nandc_set_read_loc_last(chip, reg, cw_offset, read_size, is_last_read_loc) \
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nandc_set_reg(chip, reg, \
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((cw_offset) << READ_LOCATION_OFFSET) | \
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((read_size) << READ_LOCATION_SIZE) | \
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((is_last_read_loc) << READ_LOCATION_LAST))
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/*
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* Returns the actual register address for all NAND_DEV_ registers
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* (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
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@ -316,6 +325,10 @@ struct nandc_regs {
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__le32 read_location1;
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__le32 read_location2;
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__le32 read_location3;
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__le32 read_location_last0;
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__le32 read_location_last1;
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__le32 read_location_last2;
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__le32 read_location_last3;
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__le32 erased_cw_detect_cfg_clr;
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__le32 erased_cw_detect_cfg_set;
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@ -644,6 +657,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
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return ®s->read_location2;
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case NAND_READ_LOCATION_3:
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return ®s->read_location3;
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case NAND_READ_LOCATION_LAST_CW_0:
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return ®s->read_location_last0;
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case NAND_READ_LOCATION_LAST_CW_1:
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return ®s->read_location_last1;
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case NAND_READ_LOCATION_LAST_CW_2:
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return ®s->read_location_last2;
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case NAND_READ_LOCATION_LAST_CW_3:
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return ®s->read_location_last3;
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default:
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return NULL;
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}
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@ -672,12 +693,21 @@ static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
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static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
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int cw_offset, int read_size, int is_last_read_loc)
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{
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int reg_base = NAND_READ_LOCATION_0;
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if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
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reg_base = NAND_READ_LOCATION_LAST_CW_0;
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reg_base += reg * 4;
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return nandc_set_read_loc_first(chip, reg_base, cw_offset,
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read_size, is_last_read_loc);
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if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
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return nandc_set_read_loc_last(chip, reg_base, cw_offset,
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read_size, is_last_read_loc);
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else
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return nandc_set_read_loc_first(chip, reg_base, cw_offset,
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read_size, is_last_read_loc);
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}
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/* helper to configure address register values */
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@ -698,8 +728,9 @@ static void set_address(struct qcom_nand_host *host, u16 column, int page)
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*
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* @num_cw: number of steps for the read/write operation
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* @read: read or write operation
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* @cw : which code word
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*/
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static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
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{
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struct nand_chip *chip = &host->chip;
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u32 cmd, cfg0, cfg1, ecc_bch_cfg;
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@ -737,7 +768,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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nandc_set_reg(chip, NAND_EXEC_CMD, 1);
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if (read)
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nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
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nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
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host->cw_data : host->cw_size, 1);
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}
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@ -1113,13 +1144,18 @@ static void config_nand_page_read(struct nand_chip *chip)
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* before reading each codeword in NAND page.
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*/
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static void
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config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
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config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
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{
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int reg = NAND_READ_LOCATION_0;
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if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
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reg = NAND_READ_LOCATION_LAST_CW_0;
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if (nandc->props->is_bam)
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write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
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NAND_BAM_NEXT_SGL);
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write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
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write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
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write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
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@ -1139,10 +1175,10 @@ config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
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*/
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static void
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config_nand_single_cw_page_read(struct nand_chip *chip,
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bool use_ecc)
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bool use_ecc, int cw)
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{
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config_nand_page_read(chip);
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config_nand_cw_read(chip, use_ecc);
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config_nand_cw_read(chip, use_ecc, cw);
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}
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/*
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@ -1240,7 +1276,7 @@ static int nandc_param(struct qcom_nand_host *host)
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nandc->buf_count = 512;
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memset(nandc->data_buffer, 0xff, nandc->buf_count);
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config_nand_single_cw_page_read(chip, false);
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config_nand_single_cw_page_read(chip, false, 0);
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read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
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nandc->buf_count, 0);
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@ -1517,7 +1553,7 @@ static void qcom_nandc_command(struct nand_chip *chip, unsigned int command,
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host->use_ecc = true;
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set_address(host, 0, page_addr);
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update_rw_regs(host, ecc->steps, true);
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update_rw_regs(host, ecc->steps, true, 0);
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break;
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case NAND_CMD_SEQIN:
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@ -1641,7 +1677,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
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clear_bam_transaction(nandc);
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set_address(host, host->cw_size * cw, page);
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update_rw_regs(host, 1, true);
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update_rw_regs(host, 1, true, cw);
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config_nand_page_read(chip);
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data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
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@ -1670,7 +1706,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
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nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
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}
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config_nand_cw_read(chip, false);
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config_nand_cw_read(chip, false, cw);
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read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
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reg_off += data_size1;
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@ -1909,7 +1945,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
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}
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}
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config_nand_cw_read(chip, true);
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config_nand_cw_read(chip, true, i);
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if (data_buf)
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read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
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@ -1969,9 +2005,9 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
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memset(nandc->data_buffer, 0xff, size);
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set_address(host, host->cw_size * (ecc->steps - 1), page);
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update_rw_regs(host, 1, true);
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update_rw_regs(host, 1, true, ecc->steps - 1);
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config_nand_single_cw_page_read(chip, host->use_ecc);
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config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
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read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
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@ -2036,7 +2072,7 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page)
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host->use_ecc = true;
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set_address(host, 0, page);
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update_rw_regs(host, ecc->steps, true);
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update_rw_regs(host, ecc->steps, true, 0);
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return read_page_ecc(host, NULL, chip->oob_poi, page);
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}
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@ -2060,7 +2096,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf,
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oob_buf = chip->oob_poi;
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host->use_ecc = true;
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update_rw_regs(host, ecc->steps, false);
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update_rw_regs(host, ecc->steps, false, 0);
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config_nand_page_write(chip);
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for (i = 0; i < ecc->steps; i++) {
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@ -2131,7 +2167,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip,
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oob_buf = chip->oob_poi;
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host->use_ecc = false;
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update_rw_regs(host, ecc->steps, false);
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update_rw_regs(host, ecc->steps, false, 0);
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config_nand_page_write(chip);
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for (i = 0; i < ecc->steps; i++) {
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@ -2214,7 +2250,7 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
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0, mtd->oobavail);
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set_address(host, host->cw_size * (ecc->steps - 1), page);
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update_rw_regs(host, 1, false);
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update_rw_regs(host, 1, false, 0);
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config_nand_page_write(chip);
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write_data_dma(nandc, FLASH_BUF_ACC,
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@ -2293,7 +2329,7 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
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/* prepare write */
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host->use_ecc = false;
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set_address(host, host->cw_size * (ecc->steps - 1), page);
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update_rw_regs(host, 1, false);
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update_rw_regs(host, 1, false, ecc->steps - 1);
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config_nand_page_write(chip);
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write_data_dma(nandc, FLASH_BUF_ACC,
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