Merge branch 'master' of git://git.infradead.org/users/cbou/linux-cns3xxx into devel-stable
This commit is contained in:
Коммит
50401d77ee
|
@ -17,6 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/platform_device.h>
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|
@ -107,11 +108,64 @@ static void __init cns3420_early_serial_setup(void)
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#endif
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}
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/*
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* USB
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*/
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static struct resource cns3xxx_usb_ehci_resources[] = {
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[0] = {
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.start = CNS3XXX_USB_BASE,
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.end = CNS3XXX_USB_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_USB_EHCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
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static struct platform_device cns3xxx_usb_ehci_device = {
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.name = "cns3xxx-ehci",
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.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
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.resource = cns3xxx_usb_ehci_resources,
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.dev = {
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.dma_mask = &cns3xxx_usb_ehci_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource cns3xxx_usb_ohci_resources[] = {
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[0] = {
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.start = CNS3XXX_USB_OHCI_BASE,
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.end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_USB_OHCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
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static struct platform_device cns3xxx_usb_ohci_device = {
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.name = "cns3xxx-ohci",
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.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
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.resource = cns3xxx_usb_ohci_resources,
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.dev = {
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.dma_mask = &cns3xxx_usb_ohci_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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/*
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* Initialization
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*/
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static struct platform_device *cns3420_pdevs[] __initdata = {
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&cns3420_nor_pdev,
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&cns3xxx_usb_ehci_device,
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&cns3xxx_usb_ohci_device,
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};
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static void __init cns3420_init(void)
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|
|
|
@ -17,7 +17,5 @@ extern struct sys_timer cns3xxx_timer;
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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void cns3xxx_power_off(void);
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void cns3xxx_pwr_power_up(unsigned int block);
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void cns3xxx_pwr_power_down(unsigned int block);
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#endif /* __CNS3XXX_CORE_H */
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|
|
|
@ -18,6 +18,7 @@
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#include <linux/platform_device.h>
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#include <mach/cns3xxx.h>
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#include <mach/irqs.h>
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#include <mach/pm.h>
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#include "core.h"
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#include "devices.h"
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|
|
|
@ -165,7 +165,6 @@
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#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
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#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
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#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
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#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
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#define CNS3XXX_SATA2_SIZE SZ_16M
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|
@ -184,7 +183,6 @@
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#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
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#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
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#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
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#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
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#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
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|
|
|
@ -0,0 +1,23 @@
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/*
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2004 ARM Limited
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef __CNS3XXX_PM_H
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#define __CNS3XXX_PM_H
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#include <asm/atomic.h>
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void cns3xxx_pwr_clk_en(unsigned int block);
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void cns3xxx_pwr_clk_dis(unsigned int block);
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void cns3xxx_pwr_power_up(unsigned int block);
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void cns3xxx_pwr_power_down(unsigned int block);
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extern atomic_t usb_pwr_ref;
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#endif /* __CNS3XXX_PM_H */
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|
@ -6,10 +6,14 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <asm/atomic.h>
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#include <mach/system.h>
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#include <mach/cns3xxx.h>
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#include <mach/pm.h>
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void cns3xxx_pwr_clk_en(unsigned int block)
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{
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@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block)
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reg |= (block & PM_CLK_GATE_REG_MASK);
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__raw_writel(reg, PM_CLK_GATE_REG);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
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void cns3xxx_pwr_clk_dis(unsigned int block)
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{
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u32 reg = __raw_readl(PM_CLK_GATE_REG);
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reg &= ~(block & PM_CLK_GATE_REG_MASK);
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__raw_writel(reg, PM_CLK_GATE_REG);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
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void cns3xxx_pwr_power_up(unsigned int block)
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{
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|
@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block)
|
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/* Wait for 300us for the PLL output clock locked. */
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udelay(300);
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};
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EXPORT_SYMBOL(cns3xxx_pwr_power_up);
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void cns3xxx_pwr_power_down(unsigned int block)
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{
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|
@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block)
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reg |= (block & CNS3XXX_PWR_PLL_ALL);
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__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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};
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EXPORT_SYMBOL(cns3xxx_pwr_power_down);
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||||
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static void cns3xxx_pwr_soft_rst_force(unsigned int block)
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{
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|
@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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} else {
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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__raw_writel(reg, PM_SOFT_RST_REG);
|
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reg |= (block & PM_SOFT_RST_REG_MASK);
|
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}
|
||||
|
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__raw_writel(reg, PM_SOFT_RST_REG);
|
||||
}
|
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EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
|
||||
|
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void cns3xxx_pwr_soft_rst(unsigned int block)
|
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{
|
||||
|
@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
|
|||
}
|
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cns3xxx_pwr_soft_rst_force(block);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
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void arch_reset(char mode, const char *cmd)
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{
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|
@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void)
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|
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return cpu;
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}
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EXPORT_SYMBOL(cns3xxx_cpu_clock);
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|
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atomic_t usb_pwr_ref = ATOMIC_INIT(0);
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EXPORT_SYMBOL(usb_pwr_ref);
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|
|
|
@ -41,6 +41,7 @@ config USB_ARCH_HAS_OHCI
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default y if MFD_TC6393XB
|
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default y if ARCH_W90X900
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default y if ARCH_DAVINCI_DA8XX
|
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default y if ARCH_CNS3XXX
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# PPC:
|
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default y if STB03xxx
|
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default y if PPC_MPC52xx
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|
@ -66,6 +67,7 @@ config USB_ARCH_HAS_EHCI
|
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default y if ARCH_AT91SAM9G45
|
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default y if ARCH_MXC
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default y if ARCH_OMAP3
|
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default y if ARCH_CNS3XXX
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default PCI
|
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# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
|
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|
|
|
@ -147,6 +147,14 @@ config USB_W90X900_EHCI
|
|||
---help---
|
||||
Enables support for the W90X900 USB controller
|
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|
||||
config USB_CNS3XXX_EHCI
|
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bool "Cavium CNS3XXX EHCI Module"
|
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depends on USB_EHCI_HCD && ARCH_CNS3XXX
|
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---help---
|
||||
Enable support for the CNS3XXX SOC's on-chip EHCI controller.
|
||||
It is needed for high-speed (480Mbit/sec) USB 2.0 device
|
||||
support.
|
||||
|
||||
config USB_OXU210HP_HCD
|
||||
tristate "OXU210HP HCD support"
|
||||
depends on USB
|
||||
|
@ -286,6 +294,13 @@ config USB_OHCI_HCD_SSB
|
|||
|
||||
If unsure, say N.
|
||||
|
||||
config USB_CNS3XXX_OHCI
|
||||
bool "Cavium CNS3XXX OHCI Module"
|
||||
depends on USB_OHCI_HCD && ARCH_CNS3XXX
|
||||
---help---
|
||||
Enable support for the CNS3XXX SOC's on-chip OHCI controller.
|
||||
It is needed for low-speed USB 1.0 device support.
|
||||
|
||||
config USB_OHCI_BIG_ENDIAN_DESC
|
||||
bool
|
||||
depends on USB_OHCI_HCD
|
||||
|
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright 2008 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <mach/cns3xxx.h>
|
||||
#include <mach/pm.h>
|
||||
|
||||
static int cns3xxx_ehci_init(struct usb_hcd *hcd)
|
||||
{
|
||||
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
||||
int retval;
|
||||
|
||||
/*
|
||||
* EHCI and OHCI share the same clock and power,
|
||||
* resetting twice would cause the 1st controller been reset.
|
||||
* Therefore only do power up at the first up device, and
|
||||
* power down at the last down device.
|
||||
*
|
||||
* Set USB AHB INCR length to 16
|
||||
*/
|
||||
if (atomic_inc_return(&usb_pwr_ref) == 1) {
|
||||
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
|
||||
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
|
||||
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
|
||||
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
|
||||
MISC_CHIP_CONFIG_REG);
|
||||
}
|
||||
|
||||
ehci->caps = hcd->regs;
|
||||
ehci->regs = hcd->regs
|
||||
+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
||||
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
|
||||
|
||||
hcd->has_tt = 0;
|
||||
ehci_reset(ehci);
|
||||
|
||||
retval = ehci_init(hcd);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
ehci_port_power(ehci, 0);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct hc_driver cns3xxx_ehci_hc_driver = {
|
||||
.description = hcd_name,
|
||||
.product_desc = "CNS3XXX EHCI Host Controller",
|
||||
.hcd_priv_size = sizeof(struct ehci_hcd),
|
||||
.irq = ehci_irq,
|
||||
.flags = HCD_MEMORY | HCD_USB2,
|
||||
.reset = cns3xxx_ehci_init,
|
||||
.start = ehci_run,
|
||||
.stop = ehci_stop,
|
||||
.shutdown = ehci_shutdown,
|
||||
.urb_enqueue = ehci_urb_enqueue,
|
||||
.urb_dequeue = ehci_urb_dequeue,
|
||||
.endpoint_disable = ehci_endpoint_disable,
|
||||
.endpoint_reset = ehci_endpoint_reset,
|
||||
.get_frame_number = ehci_get_frame,
|
||||
.hub_status_data = ehci_hub_status_data,
|
||||
.hub_control = ehci_hub_control,
|
||||
#ifdef CONFIG_PM
|
||||
.bus_suspend = ehci_bus_suspend,
|
||||
.bus_resume = ehci_bus_resume,
|
||||
#endif
|
||||
.relinquish_port = ehci_relinquish_port,
|
||||
.port_handed_over = ehci_port_handed_over,
|
||||
|
||||
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
|
||||
};
|
||||
|
||||
static int cns3xxx_ehci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct usb_hcd *hcd;
|
||||
const struct hc_driver *driver = &cns3xxx_ehci_hc_driver;
|
||||
struct resource *res;
|
||||
int irq;
|
||||
int retval;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Found HC with no IRQ.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
irq = res->start;
|
||||
|
||||
hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
|
||||
if (!hcd)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Found HC with no register addr.\n");
|
||||
retval = -ENODEV;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
hcd->rsrc_start = res->start;
|
||||
hcd->rsrc_len = res->end - res->start + 1;
|
||||
|
||||
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
|
||||
driver->description)) {
|
||||
dev_dbg(dev, "controller already in use\n");
|
||||
retval = -EBUSY;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
|
||||
if (hcd->regs == NULL) {
|
||||
dev_dbg(dev, "error mapping memory\n");
|
||||
retval = -EFAULT;
|
||||
goto err2;
|
||||
}
|
||||
|
||||
retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
||||
if (retval == 0)
|
||||
return retval;
|
||||
|
||||
iounmap(hcd->regs);
|
||||
err2:
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
err1:
|
||||
usb_put_hcd(hcd);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int cns3xxx_ehci_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
||||
|
||||
usb_remove_hcd(hcd);
|
||||
iounmap(hcd->regs);
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
|
||||
/*
|
||||
* EHCI and OHCI share the same clock and power,
|
||||
* resetting twice would cause the 1st controller been reset.
|
||||
* Therefore only do power up at the first up device, and
|
||||
* power down at the last down device.
|
||||
*/
|
||||
if (atomic_dec_return(&usb_pwr_ref) == 0)
|
||||
cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
|
||||
|
||||
usb_put_hcd(hcd);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_ALIAS("platform:cns3xxx-ehci");
|
||||
|
||||
static struct platform_driver cns3xxx_ehci_driver = {
|
||||
.probe = cns3xxx_ehci_probe,
|
||||
.remove = cns3xxx_ehci_remove,
|
||||
.driver = {
|
||||
.name = "cns3xxx-ehci",
|
||||
},
|
||||
};
|
|
@ -1216,6 +1216,11 @@ MODULE_LICENSE ("GPL");
|
|||
#define PLATFORM_DRIVER ehci_octeon_driver
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_CNS3XXX_EHCI
|
||||
#include "ehci-cns3xxx.c"
|
||||
#define PLATFORM_DRIVER cns3xxx_ehci_driver
|
||||
#endif
|
||||
|
||||
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
|
||||
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
|
||||
!defined(XILINX_OF_PLATFORM_DRIVER)
|
||||
|
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* Copyright 2008 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <mach/cns3xxx.h>
|
||||
#include <mach/pm.h>
|
||||
|
||||
static int __devinit
|
||||
cns3xxx_ohci_start(struct usb_hcd *hcd)
|
||||
{
|
||||
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* EHCI and OHCI share the same clock and power,
|
||||
* resetting twice would cause the 1st controller been reset.
|
||||
* Therefore only do power up at the first up device, and
|
||||
* power down at the last down device.
|
||||
*
|
||||
* Set USB AHB INCR length to 16
|
||||
*/
|
||||
if (atomic_inc_return(&usb_pwr_ref) == 1) {
|
||||
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
|
||||
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
|
||||
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
|
||||
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
|
||||
MISC_CHIP_CONFIG_REG);
|
||||
}
|
||||
|
||||
ret = ohci_init(ohci);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ohci->num_ports = 1;
|
||||
|
||||
ret = ohci_run(ohci);
|
||||
if (ret < 0) {
|
||||
err("can't start %s", hcd->self.bus_name);
|
||||
ohci_stop(hcd);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct hc_driver cns3xxx_ohci_hc_driver = {
|
||||
.description = hcd_name,
|
||||
.product_desc = "CNS3XXX OHCI Host controller",
|
||||
.hcd_priv_size = sizeof(struct ohci_hcd),
|
||||
.irq = ohci_irq,
|
||||
.flags = HCD_USB11 | HCD_MEMORY,
|
||||
.start = cns3xxx_ohci_start,
|
||||
.stop = ohci_stop,
|
||||
.shutdown = ohci_shutdown,
|
||||
.urb_enqueue = ohci_urb_enqueue,
|
||||
.urb_dequeue = ohci_urb_dequeue,
|
||||
.endpoint_disable = ohci_endpoint_disable,
|
||||
.get_frame_number = ohci_get_frame,
|
||||
.hub_status_data = ohci_hub_status_data,
|
||||
.hub_control = ohci_hub_control,
|
||||
#ifdef CONFIG_PM
|
||||
.bus_suspend = ohci_bus_suspend,
|
||||
.bus_resume = ohci_bus_resume,
|
||||
#endif
|
||||
.start_port_reset = ohci_start_port_reset,
|
||||
};
|
||||
|
||||
static int cns3xxx_ohci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct usb_hcd *hcd;
|
||||
const struct hc_driver *driver = &cns3xxx_ohci_hc_driver;
|
||||
struct resource *res;
|
||||
int irq;
|
||||
int retval;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Found HC with no IRQ.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
irq = res->start;
|
||||
|
||||
hcd = usb_create_hcd(driver, dev, dev_name(dev));
|
||||
if (!hcd)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Found HC with no register addr.\n");
|
||||
retval = -ENODEV;
|
||||
goto err1;
|
||||
}
|
||||
hcd->rsrc_start = res->start;
|
||||
hcd->rsrc_len = res->end - res->start + 1;
|
||||
|
||||
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
|
||||
driver->description)) {
|
||||
dev_dbg(dev, "controller already in use\n");
|
||||
retval = -EBUSY;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
|
||||
if (!hcd->regs) {
|
||||
dev_dbg(dev, "error mapping memory\n");
|
||||
retval = -EFAULT;
|
||||
goto err2;
|
||||
}
|
||||
|
||||
ohci_hcd_init(hcd_to_ohci(hcd));
|
||||
|
||||
retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
||||
if (retval == 0)
|
||||
return retval;
|
||||
|
||||
iounmap(hcd->regs);
|
||||
err2:
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
err1:
|
||||
usb_put_hcd(hcd);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int cns3xxx_ohci_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
||||
|
||||
usb_remove_hcd(hcd);
|
||||
iounmap(hcd->regs);
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
|
||||
/*
|
||||
* EHCI and OHCI share the same clock and power,
|
||||
* resetting twice would cause the 1st controller been reset.
|
||||
* Therefore only do power up at the first up device, and
|
||||
* power down at the last down device.
|
||||
*/
|
||||
if (atomic_dec_return(&usb_pwr_ref) == 0)
|
||||
cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
|
||||
|
||||
usb_put_hcd(hcd);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_ALIAS("platform:cns3xxx-ohci");
|
||||
|
||||
static struct platform_driver ohci_hcd_cns3xxx_driver = {
|
||||
.probe = cns3xxx_ohci_probe,
|
||||
.remove = cns3xxx_ohci_remove,
|
||||
.driver = {
|
||||
.name = "cns3xxx-ohci",
|
||||
},
|
||||
};
|
|
@ -1111,6 +1111,11 @@ MODULE_LICENSE ("GPL");
|
|||
#define PLATFORM_DRIVER ohci_octeon_driver
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_CNS3XXX_OHCI
|
||||
#include "ohci-cns3xxx.c"
|
||||
#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
|
||||
#endif
|
||||
|
||||
#if !defined(PCI_DRIVER) && \
|
||||
!defined(PLATFORM_DRIVER) && \
|
||||
!defined(OMAP1_PLATFORM_DRIVER) && \
|
||||
|
|
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