DMAENGINE: ste_dma40: allocate LCLA dynamically
Switch to allocating LCLA in memory instead of having a fixed address. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Linus Walleij
Dan Williams
Родитель
1d392a7ba4
Коммит
508849ade2
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@ -30,6 +30,12 @@
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/* Maximum iterations taken before giving up suspending a channel */
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#define D40_SUSPEND_MAX_IT 500
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/* Hardware requirement on LCLA alignment */
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#define LCLA_ALIGNMENT 0x40000
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/* Attempts before giving up to trying to get pages that are aligned */
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#define MAX_LCLA_ALLOC_ATTEMPTS 256
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/* Bit markings for allocation map */
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#define D40_ALLOC_FREE (1 << 31)
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#define D40_ALLOC_PHY (1 << 30)
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#define D40_ALLOC_LOG_FREE 0
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@ -64,9 +70,9 @@ enum d40_command {
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*/
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struct d40_lli_pool {
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void *base;
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int size;
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int size;
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/* Space for dst and src, plus an extra for padding */
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u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
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u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
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};
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/**
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@ -111,18 +117,20 @@ struct d40_desc {
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/**
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* struct d40_lcla_pool - LCLA pool settings and data.
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*
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* @base: The virtual address of LCLA.
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* @phy: Physical base address of LCLA.
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* @base_size: size of lcla.
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* @base: The virtual address of LCLA. 18 bit aligned.
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* @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
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* This pointer is only there for clean-up on error.
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* @pages: The number of pages needed for all physical channels.
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* Only used later for clean-up on error
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* @lock: Lock to protect the content in this struct.
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* @alloc_map: Mapping between physical channel and LCLA entries.
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* @alloc_map: Bitmap mapping between physical channel and LCLA entries.
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* @num_blocks: The number of entries of alloc_map. Equals to the
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* number of physical channels.
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*/
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struct d40_lcla_pool {
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void *base;
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dma_addr_t phy;
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resource_size_t base_size;
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void *base_unaligned;
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int pages;
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spinlock_t lock;
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u32 *alloc_map;
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int num_blocks;
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@ -432,13 +440,12 @@ static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
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/* Support functions for logical channels */
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static int d40_lcla_id_get(struct d40_chan *d40c,
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struct d40_lcla_pool *pool)
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static int d40_lcla_id_get(struct d40_chan *d40c)
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{
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int src_id = 0;
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int dst_id = 0;
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struct d40_log_lli *lcla_lidx_base =
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pool->base + d40c->phy_chan->num * 1024;
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d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
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int i;
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int lli_per_log = d40c->base->plat_data->llis_per_log;
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unsigned long flags;
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@ -446,24 +453,28 @@ static int d40_lcla_id_get(struct d40_chan *d40c,
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if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
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return 0;
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if (pool->num_blocks > 32)
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if (d40c->base->lcla_pool.num_blocks > 32)
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return -EINVAL;
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spin_lock_irqsave(&pool->lock, flags);
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spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
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for (i = 0; i < pool->num_blocks; i++) {
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if (!(pool->alloc_map[d40c->phy_chan->num] & (0x1 << i))) {
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pool->alloc_map[d40c->phy_chan->num] |= (0x1 << i);
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for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
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if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
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(0x1 << i))) {
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d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
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(0x1 << i);
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break;
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}
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}
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src_id = i;
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if (src_id >= pool->num_blocks)
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if (src_id >= d40c->base->lcla_pool.num_blocks)
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goto err;
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for (; i < pool->num_blocks; i++) {
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if (!(pool->alloc_map[d40c->phy_chan->num] & (0x1 << i))) {
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pool->alloc_map[d40c->phy_chan->num] |= (0x1 << i);
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for (; i < d40c->base->lcla_pool.num_blocks; i++) {
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if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
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(0x1 << i))) {
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d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
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(0x1 << i);
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break;
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}
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}
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@ -477,29 +488,13 @@ static int d40_lcla_id_get(struct d40_chan *d40c,
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d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
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d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
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spin_unlock_irqrestore(&pool->lock, flags);
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spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
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return 0;
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err:
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spin_unlock_irqrestore(&pool->lock, flags);
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spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
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return -EINVAL;
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}
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static void d40_lcla_id_put(struct d40_chan *d40c,
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struct d40_lcla_pool *pool,
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int id)
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{
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unsigned long flags;
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if (id < 0)
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return;
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d40c->lcla.src_id = -1;
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d40c->lcla.dst_id = -1;
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spin_lock_irqsave(&pool->lock, flags);
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pool->alloc_map[d40c->phy_chan->num] &= (~(0x1 << id));
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spin_unlock_irqrestore(&pool->lock, flags);
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}
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static int d40_channel_execute_command(struct d40_chan *d40c,
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enum d40_command command)
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@ -567,6 +562,7 @@ done:
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static void d40_term_all(struct d40_chan *d40c)
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{
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struct d40_desc *d40d;
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unsigned long flags;
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/* Release active descriptors */
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while ((d40d = d40_first_active_get(d40c))) {
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@ -584,10 +580,17 @@ static void d40_term_all(struct d40_chan *d40c)
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d40_desc_free(d40c, d40d);
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}
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d40_lcla_id_put(d40c, &d40c->base->lcla_pool,
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d40c->lcla.src_id);
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d40_lcla_id_put(d40c, &d40c->base->lcla_pool,
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d40c->lcla.dst_id);
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spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
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d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
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(~(0x1 << d40c->lcla.dst_id));
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d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
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(~(0x1 << d40c->lcla.src_id));
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d40c->lcla.src_id = -1;
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d40c->lcla.dst_id = -1;
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spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
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d40c->pending_tx = 0;
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d40c->busy = false;
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@ -703,7 +706,6 @@ static int d40_config_write(struct d40_chan *d40c)
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static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
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{
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if (d40d->lli_phy.dst && d40d->lli_phy.src) {
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d40_phy_lli_write(d40c->base->virtbase,
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d40c->phy_chan->num,
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@ -712,13 +714,24 @@ static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
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} else if (d40d->lli_log.dst && d40d->lli_log.src) {
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struct d40_log_lli *src = d40d->lli_log.src;
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struct d40_log_lli *dst = d40d->lli_log.dst;
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int s;
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src += d40d->lli_count;
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dst += d40d->lli_count;
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d40_log_lli_write(d40c->lcpa, d40c->lcla.src,
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d40c->lcla.dst,
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dst, src,
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d40c->base->plat_data->llis_per_log);
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s = d40_log_lli_write(d40c->lcpa,
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d40c->lcla.src, d40c->lcla.dst,
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dst, src,
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d40c->base->plat_data->llis_per_log);
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/* If s equals to zero, the job is not linked */
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if (s > 0) {
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(void) dma_map_single(d40c->base->dev, d40c->lcla.src,
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s * sizeof(struct d40_log_lli),
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DMA_TO_DEVICE);
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(void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
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s * sizeof(struct d40_log_lli),
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DMA_TO_DEVICE);
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}
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}
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d40d->lli_count += d40d->lli_tx_len;
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}
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@ -930,7 +943,8 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data)
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if (!il[row].is_error)
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dma_tc_handle(d40c);
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else
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dev_err(base->dev, "[%s] IRQ chan: %ld offset %d idx %d\n",
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dev_err(base->dev,
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"[%s] IRQ chan: %ld offset %d idx %d\n",
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__func__, chan, il[row].offset, idx);
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spin_unlock(&d40c->lock);
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@ -1089,7 +1103,8 @@ static int d40_allocate_channel(struct d40_chan *d40c)
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int j;
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int log_num;
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bool is_src;
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bool is_log = (d40c->dma_cfg.channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
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bool is_log = (d40c->dma_cfg.channel_type &
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STEDMA40_CHANNEL_IN_OPER_MODE)
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== STEDMA40_CHANNEL_IN_LOG_MODE;
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@ -1124,8 +1139,10 @@ static int d40_allocate_channel(struct d40_chan *d40c)
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for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
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int phy_num = j + event_group * 2;
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for (i = phy_num; i < phy_num + 2; i++) {
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if (d40_alloc_mask_set(&phys[i], is_src,
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0, is_log))
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if (d40_alloc_mask_set(&phys[i],
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is_src,
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0,
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is_log))
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goto found_phy;
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}
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}
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@ -1396,13 +1413,14 @@ static u32 d40_residue(struct d40_chan *d40c)
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u32 num_elt;
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if (d40c->log_num != D40_PHY_CHAN)
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num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
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num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
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>> D40_MEM_LCSP2_ECNT_POS;
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else
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num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDELT) &
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D40_SREG_ELEM_PHY_ECNT_MASK) >> D40_SREG_ELEM_PHY_ECNT_POS;
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D40_SREG_ELEM_PHY_ECNT_MASK) >>
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D40_SREG_ELEM_PHY_ECNT_POS;
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return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
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}
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@ -1455,8 +1473,10 @@ int stedma40_set_psize(struct dma_chan *chan,
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if (d40c->log_num != D40_PHY_CHAN) {
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d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
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d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
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d40c->log_def.lcsp1 |= src_psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
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d40c->log_def.lcsp3 |= dst_psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
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d40c->log_def.lcsp1 |= src_psize <<
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D40_MEM_LCSP1_SCFG_PSIZE_POS;
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d40c->log_def.lcsp3 |= dst_psize <<
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D40_MEM_LCSP1_SCFG_PSIZE_POS;
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goto out;
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}
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@ -1521,8 +1541,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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* split list into 1-length and run only in lcpa
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* space.
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*/
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if (d40_lcla_id_get(d40c,
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&d40c->base->lcla_pool) != 0)
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if (d40_lcla_id_get(d40c) != 0)
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d40d->lli_tx_len = 1;
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if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
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@ -1849,7 +1868,7 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
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* If not, split list into 1-length and run only
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* in lcpa space.
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*/
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if (d40_lcla_id_get(d40c, &d40c->base->lcla_pool) != 0)
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if (d40_lcla_id_get(d40c) != 0)
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d40d->lli_tx_len = 1;
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if (direction == DMA_FROM_DEVICE)
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@ -2476,6 +2495,78 @@ static void __init d40_hw_init(struct d40_base *base)
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}
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static int __init d40_lcla_allocate(struct d40_base *base)
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{
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unsigned long *page_list;
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int i, j;
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int ret = 0;
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/*
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* This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
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* To full fill this hardware requirement without wasting 256 kb
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* we allocate pages until we get an aligned one.
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*/
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page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
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GFP_KERNEL);
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if (!page_list) {
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ret = -ENOMEM;
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goto failure;
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}
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/* Calculating how many pages that are required */
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base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
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for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
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page_list[i] = __get_free_pages(GFP_KERNEL,
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base->lcla_pool.pages);
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if (!page_list[i]) {
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dev_err(base->dev,
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"[%s] Failed to allocate %d pages.\n",
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__func__, base->lcla_pool.pages);
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for (j = 0; j < i; j++)
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free_pages(page_list[j], base->lcla_pool.pages);
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goto failure;
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}
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if ((virt_to_phys((void *)page_list[i]) &
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(LCLA_ALIGNMENT - 1)) == 0)
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break;
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}
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for (j = 0; j < i; j++)
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free_pages(page_list[j], base->lcla_pool.pages);
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if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
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base->lcla_pool.base = (void *)page_list[i];
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} else {
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/* After many attempts, no succees with finding the correct
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* alignment try with allocating a big buffer */
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dev_warn(base->dev,
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"[%s] Failed to get %d pages @ 18 bit align.\n",
|
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__func__, base->lcla_pool.pages);
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base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
|
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base->num_phy_chans +
|
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LCLA_ALIGNMENT,
|
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GFP_KERNEL);
|
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if (!base->lcla_pool.base_unaligned) {
|
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ret = -ENOMEM;
|
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goto failure;
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}
|
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base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
|
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LCLA_ALIGNMENT);
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}
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writel(virt_to_phys(base->lcla_pool.base),
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base->virtbase + D40_DREG_LCLA);
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failure:
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kfree(page_list);
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return ret;
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}
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static int __init d40_probe(struct platform_device *pdev)
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{
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int err;
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|
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@ -2535,44 +2626,14 @@ static int __init d40_probe(struct platform_device *pdev)
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__func__);
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goto failure;
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}
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/* Get IO for logical channel link address */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcla");
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if (!res) {
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ret = -ENOENT;
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dev_err(&pdev->dev,
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"[%s] No \"lcla\" resource defined\n",
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ret = d40_lcla_allocate(base);
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if (ret) {
|
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dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
|
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__func__);
|
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goto failure;
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}
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|
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base->lcla_pool.base_size = resource_size(res);
|
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base->lcla_pool.phy = res->start;
|
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|
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if (request_mem_region(res->start, resource_size(res),
|
||||
D40_NAME " I/O lcla") == NULL) {
|
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ret = -EBUSY;
|
||||
dev_err(&pdev->dev,
|
||||
"[%s] Failed to request LCLA region 0x%x-0x%x\n",
|
||||
__func__, res->start, res->end);
|
||||
goto failure;
|
||||
}
|
||||
val = readl(base->virtbase + D40_DREG_LCLA);
|
||||
if (res->start != val && val != 0) {
|
||||
dev_warn(&pdev->dev,
|
||||
"[%s] Mismatch LCLA dma 0x%x, def 0x%x\n",
|
||||
__func__, val, res->start);
|
||||
} else
|
||||
writel(res->start, base->virtbase + D40_DREG_LCLA);
|
||||
|
||||
base->lcla_pool.base = ioremap(res->start, resource_size(res));
|
||||
if (!base->lcla_pool.base) {
|
||||
ret = -ENOMEM;
|
||||
dev_err(&pdev->dev,
|
||||
"[%s] Failed to ioremap LCLA 0x%x-0x%x\n",
|
||||
__func__, res->start, res->end);
|
||||
goto failure;
|
||||
}
|
||||
|
||||
spin_lock_init(&base->lcla_pool.lock);
|
||||
|
||||
base->lcla_pool.num_blocks = base->num_phy_chans;
|
||||
|
|
@ -2601,9 +2662,11 @@ failure:
|
|||
kmem_cache_destroy(base->desc_slab);
|
||||
if (base->virtbase)
|
||||
iounmap(base->virtbase);
|
||||
if (base->lcla_pool.phy)
|
||||
release_mem_region(base->lcla_pool.phy,
|
||||
base->lcla_pool.base_size);
|
||||
if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
|
||||
free_pages((unsigned long)base->lcla_pool.base,
|
||||
base->lcla_pool.pages);
|
||||
if (base->lcla_pool.base_unaligned)
|
||||
kfree(base->lcla_pool.base_unaligned);
|
||||
if (base->phy_lcpa)
|
||||
release_mem_region(base->phy_lcpa,
|
||||
base->lcpa_size);
|
||||
|
|
|
|||
|
|
@ -420,7 +420,7 @@ int d40_log_sg_to_lli(int lcla_id,
|
|||
return total_size;
|
||||
}
|
||||
|
||||
void d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
int d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lcla_src,
|
||||
struct d40_log_lli *lcla_dst,
|
||||
struct d40_log_lli *lli_dst,
|
||||
|
|
@ -448,4 +448,7 @@ void d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
|||
slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
|
||||
dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
|
||||
}
|
||||
|
||||
return i;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -339,12 +339,12 @@ int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
|
|||
bool term_int, dma_addr_t dev_addr, int max_len,
|
||||
int llis_per_log);
|
||||
|
||||
void d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lcla_src,
|
||||
struct d40_log_lli *lcla_dst,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int llis_per_log);
|
||||
int d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lcla_src,
|
||||
struct d40_log_lli *lcla_dst,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int llis_per_log);
|
||||
|
||||
int d40_log_sg_to_lli(int lcla_id,
|
||||
struct scatterlist *sg,
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче