arm: mmp: move pxa168 clock definition to separated file
move pxa168 clock definition to another file. Then pxa168 can choose common clock framework or private clock framework. Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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Родитель
699c9d30bc
Коммит
50d0e24499
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@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
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ifeq ($(CONFIG_COMMON_CLK), )
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obj-y += clock.o
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obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
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endif
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
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@ -0,0 +1,91 @@
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <mach/addr-map.h>
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#include "common.h"
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#include "clock.h"
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/*
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* APB clock register offsets for PXA168
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*/
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#define APBC_UART1 APBC_REG(0x000)
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#define APBC_UART2 APBC_REG(0x004)
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#define APBC_GPIO APBC_REG(0x008)
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#define APBC_PWM1 APBC_REG(0x00c)
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#define APBC_PWM2 APBC_REG(0x010)
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#define APBC_PWM3 APBC_REG(0x014)
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#define APBC_PWM4 APBC_REG(0x018)
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#define APBC_RTC APBC_REG(0x028)
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#define APBC_TWSI0 APBC_REG(0x02c)
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#define APBC_KPC APBC_REG(0x030)
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#define APBC_TWSI1 APBC_REG(0x06c)
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#define APBC_UART3 APBC_REG(0x070)
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#define APBC_SSP1 APBC_REG(0x81c)
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#define APBC_SSP2 APBC_REG(0x820)
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#define APBC_SSP3 APBC_REG(0x84c)
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#define APBC_SSP4 APBC_REG(0x858)
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#define APBC_SSP5 APBC_REG(0x85c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_LCD APMU_REG(0x04c)
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#define APMU_ETH APMU_REG(0x0fc)
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#define APMU_USB APMU_REG(0x05c)
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/* APB peripheral clocks */
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static APBC_CLK(uart1, UART1, 1, 14745600);
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static APBC_CLK(uart2, UART2, 1, 14745600);
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static APBC_CLK(uart3, UART3, 1, 14745600);
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static APBC_CLK(twsi0, TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PWM4, 1, 13000000);
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static APBC_CLK(ssp1, SSP1, 4, 0);
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static APBC_CLK(ssp2, SSP2, 4, 0);
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static APBC_CLK(ssp3, SSP3, 4, 0);
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static APBC_CLK(ssp4, SSP4, 4, 0);
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static APBC_CLK(ssp5, SSP5, 4, 0);
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static APBC_CLK(gpio, GPIO, 0, 13000000);
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static APBC_CLK(keypad, KPC, 0, 32000);
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static APBC_CLK(rtc, RTC, 8, 32768);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(lcd, LCD, 0x7f, 312000000);
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static APMU_CLK(eth, ETH, 0x09, 0);
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static APMU_CLK(usb, USB, 0x12, 0);
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/* device and clock bindings */
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static struct clk_lookup pxa168_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
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INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
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INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
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INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
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INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
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INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
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INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
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INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
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INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
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INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
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};
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void __init pxa168_clk_init(void)
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{
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clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
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}
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@ -7,3 +7,4 @@ extern void timer_init(int irq);
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extern void __init icu_init_irq(void);
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extern void __init mmp_map_io(void);
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extern void mmp_restart(char, const char *);
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extern void __init pxa168_clk_init(void);
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@ -18,8 +18,8 @@
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/addr-map.h>
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#include <mach/cputype.h>
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#include <mach/addr-map.h>
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#include <mach/regs-apbc.h>
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#include <mach/regs-apmu.h>
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#include <mach/irqs.h>
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@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
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icu_init_irq();
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}
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/* APB peripheral clocks */
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static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
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static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
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static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
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static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
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static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
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static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
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static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
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static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
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static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
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static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
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static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
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static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(lcd, LCD, 0x7f, 312000000);
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static APMU_CLK(eth, ETH, 0x09, 0);
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static APMU_CLK(usb, USB, 0x12, 0);
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/* device and clock bindings */
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static struct clk_lookup pxa168_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
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INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
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INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
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INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
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INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
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INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
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INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
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INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
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INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
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INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
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};
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static int __init pxa168_init(void)
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{
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if (cpu_is_pxa168()) {
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_addr(pxa168_mfp_addr_map);
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pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
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clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
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pxa168_clk_init();
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}
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return 0;
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@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
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/* system timer - clock enabled, 3.25MHz */
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#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
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#define APBC_TIMERS APBC_REG(0x34)
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static void __init pxa168_timer_init(void)
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{
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@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
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* ourselves instead of using clk_* API. Clock rate is defined
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* by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
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*/
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__raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
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__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
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/* 3.25MHz, bus/functional clock enabled, release reset */
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__raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
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__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
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timer_init(IRQ_PXA168_TIMER1);
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}
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