KVM/ARM changes for 4.3-rc2
- Fix timer interrupt injection after the rework that went in during the merge window - Reset the timer to zero on reboot - Make sure the TCR_EL2 RES1 bits are really set to 1 - Fix a PSCI affinity bug for non-existing vcpus -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV9VQYAAoJECPQ0LrRPXpDYFsQAIp+nIxv6LijQdq310EF7Z95 1j16vx9NfsAsNH0pwiRmx4gfNOHlPp6f30Kb1HJf2TN08Rc7TS8j4Dr3zYnZEdQj 9eNGTjCjlz93VQwKnTBvBvYkHsCEWC76pOxiYoFmnLsGc4m/OilHhohOzOZTAMFC Le07VXJwrhGHQ5bjdIMmFj+5rMj4eWfT2bYg8uVl5EUNFNkDgAMtT/Nbml90friC x+r2I9H+G8hHmemOv6hefW7l2JScLSYpqLeGdxZUtnGy9LNP3+jTD1QyqUftUPuS HtcB4zCtRk62nMupgFNV514Kf26wcwpS53vhd8aM2kxSkpr5xkUFoL+uJNT8ssIH Y+FwAOeTD0osWbmxw8Gf9d3qYzPBQSCRP3E4mCbNNNsTlMRU+Hu9au0VNBKggkfF fZ4UphCVX2C+cWaQcB40950h1F76Vx3boAfcMgiXoO+8LJx9OogDtr8+j5cBBbKU +tMngLhelsMtSCTam9c0jS6BsQfHDy3W1CQNl30cqd2RFjvygOSAqzdCMlBk0lLG 4Sq0eib1zJM+rE2OQs8SaAftyQ0kbElmM3XZB3ZiitaHgkUKV7kt9dMUG9Vfn2SE /ycgR9eoBq5P6FKhyROmL+0g824nYJmn4fwpecw1rHoRr8jyZjvpbE3VSL0aI5XW w4UYsAQSTcqM6bHpNYuu =G02h -----END PGP SIGNATURE----- Merge tag 'kvm-arm-for-4.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master KVM/ARM changes for 4.3-rc2 - Fix timer interrupt injection after the rework that went in during the merge window - Reset the timer to zero on reboot - Make sure the TCR_EL2 RES1 bits are really set to 1 - Fix a PSCI affinity bug for non-existing vcpus
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Коммит
51256484c0
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@ -126,7 +126,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
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static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
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{
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int i;
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int i, matching_cpus = 0;
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unsigned long mpidr;
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unsigned long target_affinity;
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unsigned long target_affinity_mask;
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@ -151,12 +151,16 @@ static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
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*/
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kvm_for_each_vcpu(i, tmp, kvm) {
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mpidr = kvm_vcpu_get_mpidr_aff(tmp);
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if (((mpidr & target_affinity_mask) == target_affinity) &&
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!tmp->arch.pause) {
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return PSCI_0_2_AFFINITY_LEVEL_ON;
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if ((mpidr & target_affinity_mask) == target_affinity) {
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matching_cpus++;
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if (!tmp->arch.pause)
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return PSCI_0_2_AFFINITY_LEVEL_ON;
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}
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}
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if (!matching_cpus)
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return PSCI_RET_INVALID_PARAMS;
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return PSCI_0_2_AFFINITY_LEVEL_OFF;
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}
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@ -95,6 +95,7 @@
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SCTLR_EL2_SA | SCTLR_EL2_I)
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/* TCR_EL2 Registers bits */
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#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
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#define TCR_EL2_TBI (1 << 20)
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#define TCR_EL2_PS (7 << 16)
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#define TCR_EL2_PS_40B (2 << 16)
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@ -106,9 +107,10 @@
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#define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \
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TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
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#define TCR_EL2_FLAGS (TCR_EL2_PS_40B)
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#define TCR_EL2_FLAGS (TCR_EL2_RES1 | TCR_EL2_PS_40B)
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/* VTCR_EL2 Registers bits */
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#define VTCR_EL2_RES1 (1 << 31)
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#define VTCR_EL2_PS_MASK (7 << 16)
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#define VTCR_EL2_TG0_MASK (1 << 14)
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#define VTCR_EL2_TG0_4K (0 << 14)
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@ -147,7 +149,8 @@
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*/
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#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \
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VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \
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VTCR_EL2_RES1)
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#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)
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#else
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/*
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@ -158,7 +161,8 @@
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*/
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#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \
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VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \
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VTCR_EL2_RES1)
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#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)
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#endif
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@ -199,6 +199,14 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
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*/
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timer->irq = irq;
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/*
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* The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8
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* and to 0 for ARMv7. We provide an implementation that always
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* resets the timer to be disabled and unmasked and is compliant with
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* the ARMv7 architecture.
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*/
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timer->cntv_ctl = 0;
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/*
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* Tell the VGIC that the virtual interrupt is tied to a
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* physical interrupt. We do that once per VCPU.
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@ -1144,26 +1144,11 @@ static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq,
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struct irq_phys_map *map;
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map = vgic_irq_map_search(vcpu, irq);
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/*
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* If we have a mapping, and the virtual interrupt is
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* being injected, then we must set the state to
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* active in the physical world. Otherwise the
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* physical interrupt will fire and the guest will
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* exit before processing the virtual interrupt.
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*/
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if (map) {
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int ret;
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BUG_ON(!map->active);
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vlr.hwirq = map->phys_irq;
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vlr.state |= LR_HW;
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vlr.state &= ~LR_EOI_INT;
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ret = irq_set_irqchip_state(map->irq,
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IRQCHIP_STATE_ACTIVE,
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true);
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WARN_ON(ret);
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/*
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* Make sure we're not going to sample this
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* again, as a HW-backed interrupt cannot be
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@ -1255,7 +1240,7 @@ static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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unsigned long *pa_percpu, *pa_shared;
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int i, vcpu_id;
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int i, vcpu_id, lr, ret;
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int overflow = 0;
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int nr_shared = vgic_nr_shared_irqs(dist);
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@ -1310,6 +1295,31 @@ epilog:
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*/
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clear_bit(vcpu_id, dist->irq_pending_on_cpu);
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}
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for (lr = 0; lr < vgic->nr_lr; lr++) {
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struct vgic_lr vlr;
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if (!test_bit(lr, vgic_cpu->lr_used))
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continue;
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vlr = vgic_get_lr(vcpu, lr);
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/*
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* If we have a mapping, and the virtual interrupt is
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* presented to the guest (as pending or active), then we must
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* set the state to active in the physical world. See
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* Documentation/virtual/kvm/arm/vgic-mapped-irqs.txt.
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*/
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if (vlr.state & LR_HW) {
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struct irq_phys_map *map;
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map = vgic_irq_map_search(vcpu, vlr.irq);
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ret = irq_set_irqchip_state(map->irq,
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IRQCHIP_STATE_ACTIVE,
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true);
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WARN_ON(ret);
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}
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}
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}
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static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
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