perf cs-etm: Save TRCDEVARCH register
When ETE is present save the TRCDEVARCH register and set a new magic number. It will be used to configure the decoder in a later commit. Old versions of perf will not be able to open files with this new magic number, but old files will still work with newer versions of perf. Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: James Clark <james.clark@arm.com> Acked-by: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https //lore.kernel.org/r/20210806134109.1182235-5-james.clark@arm.com [ Addressed some cosmetic suggestions by Suzuki Poulouse ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
James Clark
Arnaldo Carvalho de Melo
Родитель
c9ccc96bf6
Коммит
51ba881131
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@ -47,15 +47,17 @@ static const char *metadata_etmv3_ro[CS_ETM_PRIV_MAX] = {
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[CS_ETM_ETMIDR] = "mgmt/etmidr",
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};
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static const char *metadata_etmv4_ro[CS_ETMV4_PRIV_MAX] = {
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static const char * const metadata_etmv4_ro[] = {
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[CS_ETMV4_TRCIDR0] = "trcidr/trcidr0",
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[CS_ETMV4_TRCIDR1] = "trcidr/trcidr1",
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[CS_ETMV4_TRCIDR2] = "trcidr/trcidr2",
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[CS_ETMV4_TRCIDR8] = "trcidr/trcidr8",
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[CS_ETMV4_TRCAUTHSTATUS] = "mgmt/trcauthstatus",
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[CS_ETE_TRCDEVARCH] = "mgmt/trcdevarch"
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};
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static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
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static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu);
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static int cs_etm_set_context_id(struct auxtrace_record *itr,
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struct evsel *evsel, int cpu)
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@ -533,7 +535,7 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
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struct evlist *evlist __maybe_unused)
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{
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int i;
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int etmv3 = 0, etmv4 = 0;
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int etmv3 = 0, etmv4 = 0, ete = 0;
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struct perf_cpu_map *event_cpus = evlist->core.cpus;
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struct perf_cpu_map *online_cpus = perf_cpu_map__new(NULL);
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@ -544,7 +546,9 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
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!cpu_map__has(online_cpus, i))
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continue;
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if (cs_etm_is_etmv4(itr, i))
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if (cs_etm_is_ete(itr, i))
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ete++;
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else if (cs_etm_is_etmv4(itr, i))
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etmv4++;
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else
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etmv3++;
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@ -555,7 +559,9 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
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if (!cpu_map__has(online_cpus, i))
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continue;
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if (cs_etm_is_etmv4(itr, i))
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if (cs_etm_is_ete(itr, i))
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ete++;
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else if (cs_etm_is_etmv4(itr, i))
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etmv4++;
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else
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etmv3++;
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@ -565,6 +571,7 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
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perf_cpu_map__put(online_cpus);
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return (CS_ETM_HEADER_SIZE +
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(ete * CS_ETE_PRIV_SIZE) +
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(etmv4 * CS_ETMV4_PRIV_SIZE) +
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(etmv3 * CS_ETMV3_PRIV_SIZE));
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}
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@ -607,6 +614,27 @@ static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path)
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return val;
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}
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#define TRCDEVARCH_ARCHPART_SHIFT 0
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#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0)
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#define TRCDEVARCH_ARCHPART(x) (((x) & TRCDEVARCH_ARCHPART_MASK) >> TRCDEVARCH_ARCHPART_SHIFT)
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#define TRCDEVARCH_ARCHVER_SHIFT 12
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#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12)
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#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT)
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static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu)
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{
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struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
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struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
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int trcdevarch = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETE_TRCDEVARCH]);
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/*
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* ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13.
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* See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h
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*/
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return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13;
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}
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static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, int cpu)
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{
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struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
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@ -640,7 +668,18 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
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struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
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/* first see what kind of tracer this cpu is affined to */
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if (cs_etm_is_etmv4(itr, cpu)) {
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if (cs_etm_is_ete(itr, cpu)) {
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magic = __perf_cs_ete_magic;
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/* ETE uses the same registers as ETMv4 plus TRCDEVARCH */
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cs_etm_save_etmv4_header(&info->priv[*offset], itr, cpu);
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info->priv[*offset + CS_ETE_TRCDEVARCH] =
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cs_etm_get_ro(cs_etm_pmu, cpu,
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metadata_etmv4_ro[CS_ETE_TRCDEVARCH]);
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/* How much space was used */
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increment = CS_ETE_PRIV_MAX;
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nr_trc_params = CS_ETE_PRIV_MAX - CS_ETM_COMMON_BLK_MAX_V1;
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} else if (cs_etm_is_etmv4(itr, cpu)) {
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magic = __perf_cs_etmv4_magic;
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cs_etm_save_etmv4_header(&info->priv[*offset], itr, cpu);
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@ -2521,6 +2521,7 @@ static const char * const cs_etmv4_priv_fmts[] = {
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[CS_ETMV4_TRCIDR2] = " TRCIDR2 %llx\n",
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[CS_ETMV4_TRCIDR8] = " TRCIDR8 %llx\n",
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[CS_ETMV4_TRCAUTHSTATUS] = " TRCAUTHSTATUS %llx\n",
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[CS_ETE_TRCDEVARCH] = " TRCDEVARCH %llx\n"
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};
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static const char * const param_unk_fmt =
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@ -2580,10 +2581,15 @@ static int cs_etm__print_cpu_metadata_v1(__u64 *val, int *offset)
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else
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fprintf(stdout, cs_etm_priv_fmts[j], val[i]);
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}
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} else if (magic == __perf_cs_etmv4_magic) {
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} else if (magic == __perf_cs_etmv4_magic || magic == __perf_cs_ete_magic) {
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/*
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* ETE and ETMv4 can be printed in the same block because the number of parameters
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* is saved and they share the list of parameter names. ETE is also only supported
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* in V1 files.
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*/
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for (j = 0; j < total_params; j++, i++) {
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/* if newer record - could be excess params */
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if (j >= CS_ETMV4_PRIV_MAX)
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if (j >= CS_ETE_PRIV_MAX)
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fprintf(stdout, param_unk_fmt, j, val[i]);
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else
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fprintf(stdout, cs_etmv4_priv_fmts[j], val[i]);
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@ -2952,6 +2958,11 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
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/* The traceID is our handle */
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trcidr_idx = CS_ETMV4_TRCTRACEIDR;
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} else if (ptr[i] == __perf_cs_ete_magic) {
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metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETE_PRIV_MAX, -1);
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/* ETE shares first part of metadata with ETMv4 */
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trcidr_idx = CS_ETMV4_TRCTRACEIDR;
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}
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if (!metadata[j]) {
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@ -76,6 +76,15 @@ enum {
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/* define fixed version 0 length - allow new format reader to read old files. */
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#define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
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/*
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* ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
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* added in header V1
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*/
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enum {
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CS_ETE_TRCDEVARCH = CS_ETMV4_PRIV_MAX,
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CS_ETE_PRIV_MAX
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};
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/*
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* ETMv3 exception encoding number:
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* See Embedded Trace Macrocell specification (ARM IHI 0014Q)
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@ -187,8 +196,10 @@ struct cs_etm_packet_queue {
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#define __perf_cs_etmv3_magic 0x3030303030303030ULL
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#define __perf_cs_etmv4_magic 0x4040404040404040ULL
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#define __perf_cs_ete_magic 0x5050505050505050ULL
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#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
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#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
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#define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64))
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#ifdef HAVE_CSTRACE_SUPPORT
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int cs_etm__process_auxtrace_info(union perf_event *event,
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