Allwinner clocks additions for 4.7
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXI4/UAAoJEBx+YmzsjxAgJ9sP/iAKVRDJt/ng0Zw+niGC8EMZ AdqXCSbRj7bwnIyT+0ETEFIhaUTXVEg0wIfEQxPKIMOatL51OlR0Iuwviji43IeF oJUDQHSuKOZav7mlLKuEQJIOQBlqbMqjSecFyPN7yqRS9+qD+bDxWE54wXxapXPN QT/RT7662cSUWzmeUFE5OcBd8AIHQp32ozeWFA7kezfExUqQXHopFi98e0erba+x Z74cfC7aNOce3BcgpiyY0UdfHWIGZxkTEFp6KELX92gCrGVghQ+SjOTyp6FIcU/N Y+3BEsjMEByRfhxokKdmReoOAHlHJOmPlERa7vUqsksbEHYtNbbQxRMag76R00hI BdOASfvHcJVSeQQWKgOcdHoHCZcNubgDMjqv0aRY1ZX7MeVg1qxw+XEhsunUTNay Ifjq2qRLY2dGOioUk9adCorr3Z+Of9uPjB1VTQSbrKgJLe7fMdXp8ww6iNxQZ9eo x5JtjaJ2sREFQNGK8WzpImCJ5g6Oa0GQ7C4Lg/Y3obFRnsBiGDKLJDwmbHkhO/ZK i8N7AXIum0k+Tad8ndLLTahKJ4iH46E2RKDbieCzRIW0oqnB+nAzsm4a2SG3AJFR hB11sL3WCugDDJHCQvzCzdadHXSOYJC3g30r/WC7jr6ri0c7IHXQ0OHHhF1d36Ms rzWKUbSyINwTXtjijfiS =ttF/ -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent
This commit is contained in:
Stephen Boyd
Коммит
51de8760fb
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@ -10,6 +10,7 @@ Required properties:
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"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
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"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
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"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
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"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
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@ -64,6 +65,7 @@ Required properties:
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"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
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"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
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"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
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"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
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"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
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"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
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"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
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@ -73,6 +75,7 @@ Required properties:
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"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
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@ -81,6 +84,7 @@ Required properties:
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"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
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"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
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"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
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"allwinner,sun6i-a31-display-clk" - for the display clocks
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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@ -11,6 +11,8 @@ obj-y += clk-a10-ve.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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obj-y += clk-sun4i-pll3.o
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obj-y += clk-sun4i-tcon-ch1.o
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obj-y += clk-sun8i-bus-gates.o
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obj-y += clk-sun8i-mbus.o
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obj-y += clk-sun9i-core.o
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@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node)
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clk = clk_register_composite(NULL, clk_name, parents, i,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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&gate->hw, &clk_gate_ops, 0);
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&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
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if (IS_ERR(clk))
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goto err_free_gate;
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@ -0,0 +1,98 @@
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/*
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define SUN4I_A10_PLL3_GATE_BIT 31
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#define SUN4I_A10_PLL3_DIV_WIDTH 7
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#define SUN4I_A10_PLL3_DIV_SHIFT 0
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static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
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static void __init sun4i_a10_pll3_setup(struct device_node *node)
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{
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const char *clk_name = node->name, *parent;
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struct clk_multiplier *mult;
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struct clk_gate *gate;
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struct resource res;
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void __iomem *reg;
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struct clk *clk;
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int ret;
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent = of_clk_get_parent_name(node, 0);
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg)) {
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pr_err("%s: Could not map the clock registers\n", clk_name);
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return;
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}
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_unmap;
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gate->reg = reg;
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gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
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gate->lock = &sun4i_a10_pll3_lock;
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mult = kzalloc(sizeof(*mult), GFP_KERNEL);
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if (!mult)
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goto err_free_gate;
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mult->reg = reg;
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mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
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mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
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mult->lock = &sun4i_a10_pll3_lock;
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clk = clk_register_composite(NULL, clk_name,
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&parent, 1,
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NULL, NULL,
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&mult->hw, &clk_multiplier_ops,
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&gate->hw, &clk_gate_ops,
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0);
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if (IS_ERR(clk)) {
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pr_err("%s: Couldn't register the clock\n", clk_name);
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goto err_free_mult;
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}
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ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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if (ret) {
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pr_err("%s: Couldn't register DT provider\n",
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clk_name);
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goto err_clk_unregister;
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}
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return;
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err_clk_unregister:
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clk_unregister_composite(clk);
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err_free_mult:
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kfree(mult);
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err_free_gate:
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kfree(gate);
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err_unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
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sun4i_a10_pll3_setup);
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@ -0,0 +1,300 @@
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/*
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define TCON_CH1_SCLK2_PARENTS 4
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#define TCON_CH1_SCLK2_GATE_BIT BIT(31)
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#define TCON_CH1_SCLK2_MUX_MASK 3
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#define TCON_CH1_SCLK2_MUX_SHIFT 24
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#define TCON_CH1_SCLK2_DIV_MASK 0xf
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#define TCON_CH1_SCLK2_DIV_SHIFT 0
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#define TCON_CH1_SCLK1_GATE_BIT BIT(15)
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#define TCON_CH1_SCLK1_HALF_BIT BIT(11)
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struct tcon_ch1_clk {
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struct clk_hw hw;
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spinlock_t lock;
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void __iomem *reg;
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};
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#define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
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static void tcon_ch1_disable(struct clk_hw *hw)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&tclk->lock, flags);
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reg = readl(tclk->reg);
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reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
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writel(reg, tclk->reg);
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spin_unlock_irqrestore(&tclk->lock, flags);
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}
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static int tcon_ch1_enable(struct clk_hw *hw)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&tclk->lock, flags);
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reg = readl(tclk->reg);
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reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
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writel(reg, tclk->reg);
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spin_unlock_irqrestore(&tclk->lock, flags);
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return 0;
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}
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static int tcon_ch1_is_enabled(struct clk_hw *hw)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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u32 reg;
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reg = readl(tclk->reg);
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return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
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}
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static u8 tcon_ch1_get_parent(struct clk_hw *hw)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 reg;
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reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
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reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
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if (reg >= num_parents)
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return -EINVAL;
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return reg;
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}
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static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&tclk->lock, flags);
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reg = readl(tclk->reg);
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reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
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reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
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writel(reg, tclk->reg);
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spin_unlock_irqrestore(&tclk->lock, flags);
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return 0;
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};
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static unsigned long tcon_ch1_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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u8 *div,
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bool *half)
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{
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unsigned long best_rate = 0;
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u8 best_m = 0, m;
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bool is_double;
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for (m = 1; m < 16; m++) {
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u8 d;
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for (d = 1; d < 3; d++) {
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unsigned long tmp_rate;
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tmp_rate = parent_rate / m / d;
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if (tmp_rate > rate)
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continue;
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if (!best_rate ||
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(rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = m;
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is_double = d;
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}
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}
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}
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if (div && half) {
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*div = best_m;
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*half = is_double;
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}
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return best_rate;
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}
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static int tcon_ch1_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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long best_rate = -EINVAL;
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int i;
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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unsigned long parent_rate;
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unsigned long tmp_rate;
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struct clk_hw *parent;
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
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NULL, NULL);
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if (best_rate < 0 ||
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(req->rate - tmp_rate) < (req->rate - best_rate)) {
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best_rate = tmp_rate;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent;
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}
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}
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if (best_rate < 0)
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return best_rate;
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req->rate = best_rate;
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return 0;
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}
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static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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u32 reg;
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reg = readl(tclk->reg);
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parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
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if (reg & TCON_CH1_SCLK1_HALF_BIT)
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parent_rate /= 2;
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return parent_rate;
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}
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static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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unsigned long flags;
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bool half;
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u8 div_m;
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u32 reg;
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|
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tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
|
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|
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spin_lock_irqsave(&tclk->lock, flags);
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reg = readl(tclk->reg);
|
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reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
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reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
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if (half)
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reg |= TCON_CH1_SCLK1_HALF_BIT;
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writel(reg, tclk->reg);
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spin_unlock_irqrestore(&tclk->lock, flags);
|
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|
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return 0;
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}
|
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|
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static const struct clk_ops tcon_ch1_ops = {
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.disable = tcon_ch1_disable,
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.enable = tcon_ch1_enable,
|
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.is_enabled = tcon_ch1_is_enabled,
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|
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.get_parent = tcon_ch1_get_parent,
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.set_parent = tcon_ch1_set_parent,
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|
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.determine_rate = tcon_ch1_determine_rate,
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.recalc_rate = tcon_ch1_recalc_rate,
|
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.set_rate = tcon_ch1_set_rate,
|
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};
|
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|
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static void __init tcon_ch1_setup(struct device_node *node)
|
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{
|
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const char *parents[TCON_CH1_SCLK2_PARENTS];
|
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const char *clk_name = node->name;
|
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struct clk_init_data init;
|
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struct tcon_ch1_clk *tclk;
|
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struct resource res;
|
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struct clk *clk;
|
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void __iomem *reg;
|
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int ret;
|
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|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg)) {
|
||||
pr_err("%s: Could not map the clock registers\n", clk_name);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
|
||||
if (ret != TCON_CH1_SCLK2_PARENTS) {
|
||||
pr_err("%s Could not retrieve the parents\n", clk_name);
|
||||
goto err_unmap;
|
||||
}
|
||||
|
||||
tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
|
||||
if (!tclk)
|
||||
goto err_unmap;
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = &tcon_ch1_ops;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = TCON_CH1_SCLK2_PARENTS;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
|
||||
tclk->reg = reg;
|
||||
tclk->hw.init = &init;
|
||||
spin_lock_init(&tclk->lock);
|
||||
|
||||
clk = clk_register(NULL, &tclk->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: Couldn't register the clock\n", clk_name);
|
||||
goto err_free_data;
|
||||
}
|
||||
|
||||
ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
if (ret) {
|
||||
pr_err("%s: Couldn't register our clock provider\n", clk_name);
|
||||
goto err_unregister_clk;
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
err_unregister_clk:
|
||||
clk_unregister(clk);
|
||||
err_free_data:
|
||||
kfree(tclk);
|
||||
err_unmap:
|
||||
iounmap(reg);
|
||||
of_address_to_resource(node, 0, &res);
|
||||
release_mem_region(res.start, resource_size(&res));
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",
|
||||
tcon_ch1_setup);
|
||||
|
|
@ -106,7 +106,7 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
|
|||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* one clock/reset pair per word */
|
||||
count = DIV_ROUND_UP((r->end - r->start + 1), SUN9I_MMC_WIDTH);
|
||||
count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
|
||||
data->membase = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
|
|
|||
|
|
@ -523,21 +523,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
|
|||
.enable = 31,
|
||||
.table = &sun4i_pll5_config,
|
||||
.getter = sun4i_get_pll5_factors,
|
||||
.name = "pll5",
|
||||
};
|
||||
|
||||
static const struct factors_data sun4i_pll6_data __initconst = {
|
||||
.enable = 31,
|
||||
.table = &sun4i_pll5_config,
|
||||
.getter = sun4i_get_pll5_factors,
|
||||
.name = "pll6",
|
||||
};
|
||||
|
||||
static const struct factors_data sun6i_a31_pll6_data __initconst = {
|
||||
.enable = 31,
|
||||
.table = &sun6i_a31_pll6_config,
|
||||
.getter = sun6i_a31_get_pll6_factors,
|
||||
.name = "pll6x2",
|
||||
};
|
||||
|
||||
static const struct factors_data sun5i_a13_ahb_data __initconst = {
|
||||
|
|
@ -933,7 +924,7 @@ static const struct divs_data pll5_divs_data __initconst = {
|
|||
};
|
||||
|
||||
static const struct divs_data pll6_divs_data __initconst = {
|
||||
.factors = &sun4i_pll6_data,
|
||||
.factors = &sun4i_pll5_data,
|
||||
.ndivs = 4,
|
||||
.div = {
|
||||
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
|
||||
|
|
@ -975,6 +966,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
|
|||
struct clk_gate *gate = NULL;
|
||||
struct clk_fixed_factor *fix_factor;
|
||||
struct clk_divider *divider;
|
||||
struct factors_data factors = *data->factors;
|
||||
char *derived_name = NULL;
|
||||
void __iomem *reg;
|
||||
int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
|
||||
int flags, clkflags;
|
||||
|
|
@ -983,11 +976,37 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
|
|||
if (data->ndivs)
|
||||
ndivs = data->ndivs;
|
||||
|
||||
/* Try to find a name for base factor clock */
|
||||
for (i = 0; i < ndivs; i++) {
|
||||
if (data->div[i].self) {
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
i, &factors.name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* If we don't have a .self clk use the first output-name up to '_' */
|
||||
if (factors.name == NULL) {
|
||||
char *endp;
|
||||
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
0, &clk_name);
|
||||
endp = strchr(clk_name, '_');
|
||||
if (endp) {
|
||||
derived_name = kstrndup(clk_name, endp - clk_name,
|
||||
GFP_KERNEL);
|
||||
factors.name = derived_name;
|
||||
} else {
|
||||
factors.name = clk_name;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set up factor clock that we will be dividing */
|
||||
pclk = sunxi_factors_clk_setup(node, data->factors);
|
||||
pclk = sunxi_factors_clk_setup(node, &factors);
|
||||
if (!pclk)
|
||||
return NULL;
|
||||
|
||||
parent = __clk_get_name(pclk);
|
||||
kfree(derived_name);
|
||||
|
||||
reg = of_iomap(node, 0);
|
||||
if (!reg) {
|
||||
|
|
@ -1127,3 +1146,41 @@ static void __init sun6i_pll6_clk_setup(struct device_node *node)
|
|||
}
|
||||
CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
|
||||
sun6i_pll6_clk_setup);
|
||||
|
||||
/*
|
||||
* sun6i display
|
||||
*
|
||||
* rate = parent_rate / (m + 1);
|
||||
*/
|
||||
static void sun6i_display_factors(struct factors_request *req)
|
||||
{
|
||||
u8 m;
|
||||
|
||||
if (req->rate > req->parent_rate)
|
||||
req->rate = req->parent_rate;
|
||||
|
||||
m = DIV_ROUND_UP(req->parent_rate, req->rate);
|
||||
|
||||
req->rate = req->parent_rate / m;
|
||||
req->m = m - 1;
|
||||
}
|
||||
|
||||
static const struct clk_factors_config sun6i_display_config = {
|
||||
.mshift = 0,
|
||||
.mwidth = 4,
|
||||
};
|
||||
|
||||
static const struct factors_data sun6i_display_data __initconst = {
|
||||
.enable = 31,
|
||||
.mux = 24,
|
||||
.muxmask = BIT(2) | BIT(1) | BIT(0),
|
||||
.table = &sun6i_display_config,
|
||||
.getter = sun6i_display_factors,
|
||||
};
|
||||
|
||||
static void __init sun6i_display_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_factors_clk_setup(node, &sun6i_display_data);
|
||||
}
|
||||
CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
|
||||
sun6i_display_setup);
|
||||
|
|
|
|||
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