dt-bindings: spmi: convert QCOM PMIC SPMI bindings to yaml
Convert Qualcomm PMIC SPMI binding to yaml format. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211227170151.73116-1-david@ixit.cz
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David Heidelberg
Rob Herring
Родитель
1d7aff7788
Коммит
52077d8233
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@ -59,7 +59,7 @@ Required properties for peripheral child nodes:
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Optional properties for peripheral child nodes:
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- interrupts: Interrupts are specified as a 4-tuple. For more information
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see:
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Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
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Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
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- interrupt-names: Corresponding interrupt name to the interrupts property
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Each child node of SPMI slave id represents a function of the PMIC. In the
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@ -1,65 +0,0 @@
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Qualcomm SPMI Controller (PMIC Arbiter)
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The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control a single SPMI master.
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The PMIC Arbiter can also act as an interrupt controller, providing interrupts
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to slave devices.
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See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI
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controller binding requirements for child nodes.
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See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
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generic interrupt controller binding documentation.
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Required properties:
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- compatible : should be "qcom,spmi-pmic-arb".
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- reg-names : must contain:
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"core" - core registers
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"intr" - interrupt controller registers
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"cnfg" - configuration registers
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Registers used only for V2 PMIC Arbiter:
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"chnls" - tx-channel per virtual slave registers.
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"obsrvr" - rx-channel (called observer) per virtual slave registers.
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- reg : address + size pairs describing the PMIC arb register sets; order must
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correspond with the order of entries in reg-names
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- #address-cells : must be set to 2
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- #size-cells : must be set to 0
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- qcom,ee : indicates the active Execution Environment identifier (0-5)
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- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
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- interrupts : interrupt list for the PMIC Arb controller, must contain a
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single interrupt entry for the peripheral interrupt
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- interrupt-names : corresponding interrupt names for the interrupts
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listed in the 'interrupts' property, must contain:
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"periph_irq" - summary interrupt for PMIC peripherals
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- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
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- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
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cell 1: slave ID for the requested interrupt (0-15)
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cell 2: peripheral ID for requested interrupt (0-255)
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cell 3: the requested peripheral interrupt (0-7)
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cell 4: interrupt flags indicating level-sense information, as defined in
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dt-bindings/interrupt-controller/irq.h
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Example:
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spmi {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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@ -0,0 +1,120 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SPMI Controller (PMIC Arbiter)
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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description: |
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The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control a single SPMI master.
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The PMIC Arbiter can also act as an interrupt controller, providing interrupts
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to slave devices.
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allOf:
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- $ref: spmi.yaml
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properties:
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compatible:
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const: qcom,spmi-pmic-arb
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reg:
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oneOf:
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- items: # V1
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- description: core registers
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- description: interrupt controller registers
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- description: configuration registers
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- items: # V2
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- description: core registers
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- description: tx-channel per virtual slave regosters
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- description: rx-channel (called observer) per virtual slave registers
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- description: interrupt controller registers
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- description: configuration registers
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reg-names:
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oneOf:
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- items:
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- const: core
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- const: intr
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- const: cnfg
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- items:
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- const: core
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- const: chnls
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- const: obsrvr
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- const: intr
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- const: cnfg
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interrupts:
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maxItems: 1
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interrupt-names:
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const: periph_irq
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interrupt-controller: true
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'#address-cells': true
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'#interrupt-cells':
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const: 4
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description: |
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cell 1: slave ID for the requested interrupt (0-15)
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cell 2: peripheral ID for requested interrupt (0-255)
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cell 3: the requested peripheral interrupt (0-7)
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cell 4: interrupt flags indicating level-sense information,
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as defined in dt-bindings/interrupt-controller/irq.h
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'#size-cells': true
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qcom,ee:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 5
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description: >
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indicates the active Execution Environment identifier
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qcom,channel:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 5
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description: >
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which of the PMIC Arb provided channels to use for accesses
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required:
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- compatible
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- reg-names
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- interrupts
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- interrupt-names
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- '#interrupt-cells'
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- qcom,ee
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- qcom,channel
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unevaluatedProperties: false
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examples:
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- |
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spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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