ASoC: q6afe-clocks: add q6afe clock controller
q6afe already exposes lpass clocks, however this was not presented as proper clock controller driver. This patch basically adds clock controller support for q6afe clocks. This is useful for other drivers like lpass digital codec or lpass lowpower island drivers to request or vote for these clocks. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200910135708.14842-3-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla
Mark Brown
Родитель
4e398353a7
Коммит
520a1c396d
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@ -63,6 +63,9 @@ config SND_SOC_QDSP6_AFE
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config SND_SOC_QDSP6_AFE_DAI
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tristate
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config SND_SOC_QDSP6_AFE_CLOCKS
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tristate
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config SND_SOC_QDSP6_ADM
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tristate
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@ -83,6 +86,7 @@ config SND_SOC_QDSP6
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select SND_SOC_QDSP6_CORE
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select SND_SOC_QDSP6_AFE
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select SND_SOC_QDSP6_AFE_DAI
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select SND_SOC_QDSP6_AFE_CLOCKS
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select SND_SOC_QDSP6_ADM
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select SND_SOC_QDSP6_ROUTING
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select SND_SOC_QDSP6_ASM
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@ -3,6 +3,7 @@ obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += q6dsp-common.o
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obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o
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obj-$(CONFIG_SND_SOC_QDSP6_AFE) += q6afe.o
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obj-$(CONFIG_SND_SOC_QDSP6_AFE_DAI) += q6afe-dai.o
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obj-$(CONFIG_SND_SOC_QDSP6_AFE_CLOCKS) += q6afe-clocks.o
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obj-$(CONFIG_SND_SOC_QDSP6_ADM) += q6adm.o
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obj-$(CONFIG_SND_SOC_QDSP6_ROUTING) += q6routing.o
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obj-$(CONFIG_SND_SOC_QDSP6_ASM) += q6asm.o
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@ -0,0 +1,270 @@
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// SPDX-License-Identifier: GPL-1.0
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// Copyright (c) 2020, Linaro Limited
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include "q6afe.h"
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#define Q6AFE_CLK(id) &(struct q6afe_clk) { \
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.clk_id = id, \
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.afe_clk_id = Q6AFE_##id, \
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.name = #id, \
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.attributes = LPASS_CLK_ATTRIBUTE_COUPLE_NO, \
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.hw.init = &(struct clk_init_data) { \
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.ops = &clk_q6afe_ops, \
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.name = #id, \
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}, \
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}
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#define Q6AFE_VOTE_CLK(id, blkid, n) &(struct q6afe_clk) { \
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.clk_id = id, \
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.afe_clk_id = blkid, \
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.name = #n, \
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.hw.init = &(struct clk_init_data) { \
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.ops = &clk_vote_q6afe_ops, \
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.name = #id, \
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}, \
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}
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struct q6afe_clk {
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struct device *dev;
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int clk_id;
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int afe_clk_id;
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char *name;
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int attributes;
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int rate;
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uint32_t handle;
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struct clk_hw hw;
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};
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#define to_q6afe_clk(_hw) container_of(_hw, struct q6afe_clk, hw)
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struct q6afe_cc {
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struct device *dev;
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struct q6afe_clk **clks;
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int num_clks;
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};
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static int clk_q6afe_prepare(struct clk_hw *hw)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
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Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate);
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}
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static void clk_q6afe_unprepare(struct clk_hw *hw)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
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Q6AFE_LPASS_CLK_ROOT_DEFAULT, 0);
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}
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static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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clk->rate = rate;
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return 0;
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}
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static unsigned long clk_q6afe_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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return clk->rate;
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}
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static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static const struct clk_ops clk_q6afe_ops = {
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.prepare = clk_q6afe_prepare,
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.unprepare = clk_q6afe_unprepare,
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.set_rate = clk_q6afe_set_rate,
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.round_rate = clk_q6afe_round_rate,
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.recalc_rate = clk_q6afe_recalc_rate,
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};
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static int clk_vote_q6afe_block(struct clk_hw *hw)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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return q6afe_vote_lpass_core_hw(clk->dev, clk->afe_clk_id,
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clk->name, &clk->handle);
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}
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static void clk_unvote_q6afe_block(struct clk_hw *hw)
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{
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struct q6afe_clk *clk = to_q6afe_clk(hw);
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q6afe_unvote_lpass_core_hw(clk->dev, clk->afe_clk_id, clk->handle);
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}
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static const struct clk_ops clk_vote_q6afe_ops = {
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.prepare = clk_vote_q6afe_block,
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.unprepare = clk_unvote_q6afe_block,
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};
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struct q6afe_clk *q6afe_clks[Q6AFE_MAX_CLK_ID] = {
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[LPASS_CLK_ID_PRI_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
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[LPASS_CLK_ID_PRI_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
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[LPASS_CLK_ID_SEC_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
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[LPASS_CLK_ID_SEC_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
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[LPASS_CLK_ID_TER_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
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[LPASS_CLK_ID_TER_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
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[LPASS_CLK_ID_QUAD_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
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[LPASS_CLK_ID_QUAD_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
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[LPASS_CLK_ID_SPEAKER_I2S_IBIT] =
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Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
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[LPASS_CLK_ID_SPEAKER_I2S_EBIT] =
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Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
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[LPASS_CLK_ID_SPEAKER_I2S_OSR] =
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Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
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[LPASS_CLK_ID_QUI_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
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[LPASS_CLK_ID_QUI_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
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[LPASS_CLK_ID_SEN_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
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[LPASS_CLK_ID_SEN_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
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[LPASS_CLK_ID_INT0_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
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[LPASS_CLK_ID_INT1_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
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[LPASS_CLK_ID_INT2_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
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[LPASS_CLK_ID_INT3_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
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[LPASS_CLK_ID_INT4_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
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[LPASS_CLK_ID_INT5_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
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[LPASS_CLK_ID_INT6_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
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[LPASS_CLK_ID_QUI_MI2S_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
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[LPASS_CLK_ID_PRI_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT),
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[LPASS_CLK_ID_PRI_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT),
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[LPASS_CLK_ID_SEC_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT),
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[LPASS_CLK_ID_SEC_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT),
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[LPASS_CLK_ID_TER_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT),
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[LPASS_CLK_ID_TER_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT),
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[LPASS_CLK_ID_QUAD_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT),
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[LPASS_CLK_ID_QUAD_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT),
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[LPASS_CLK_ID_QUIN_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT),
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[LPASS_CLK_ID_QUIN_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT),
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[LPASS_CLK_ID_QUI_PCM_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR),
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[LPASS_CLK_ID_PRI_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT),
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[LPASS_CLK_ID_PRI_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT),
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[LPASS_CLK_ID_SEC_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT),
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[LPASS_CLK_ID_SEC_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT),
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[LPASS_CLK_ID_TER_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT),
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[LPASS_CLK_ID_TER_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT),
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[LPASS_CLK_ID_QUAD_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT),
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[LPASS_CLK_ID_QUAD_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT),
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[LPASS_CLK_ID_QUIN_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT),
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[LPASS_CLK_ID_QUIN_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT),
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[LPASS_CLK_ID_QUIN_TDM_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR),
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[LPASS_CLK_ID_MCLK_1] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_1),
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[LPASS_CLK_ID_MCLK_2] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_2),
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[LPASS_CLK_ID_MCLK_3] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_3),
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[LPASS_CLK_ID_MCLK_4] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_4),
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[LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE] =
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Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
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[LPASS_CLK_ID_INT_MCLK_0] = Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0),
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[LPASS_CLK_ID_INT_MCLK_1] = Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1),
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[LPASS_CLK_ID_WSA_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
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[LPASS_CLK_ID_WSA_CORE_NPL_MCLK] =
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Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
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[LPASS_CLK_ID_VA_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
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[LPASS_CLK_ID_TX_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
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[LPASS_CLK_ID_TX_CORE_NPL_MCLK] =
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Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
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[LPASS_CLK_ID_RX_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
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[LPASS_CLK_ID_RX_CORE_NPL_MCLK] =
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Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
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[LPASS_CLK_ID_VA_CORE_2X_MCLK] =
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Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
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[LPASS_HW_AVTIMER_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
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Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
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"LPASS_AVTIMER_MACRO"),
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[LPASS_HW_MACRO_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_MACRO_VOTE,
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Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
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"LPASS_HW_MACRO"),
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[LPASS_HW_DCODEC_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
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Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
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"LPASS_HW_DCODEC"),
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};
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static struct clk_hw *q6afe_of_clk_hw_get(struct of_phandle_args *clkspec,
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void *data)
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{
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struct q6afe_cc *cc = data;
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unsigned int idx = clkspec->args[0];
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unsigned int attr = clkspec->args[1];
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if (idx >= cc->num_clks || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
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dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
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return ERR_PTR(-EINVAL);
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}
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if (cc->clks[idx]) {
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cc->clks[idx]->attributes = attr;
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return &cc->clks[idx]->hw;
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}
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return ERR_PTR(-ENOENT);
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}
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static int q6afe_clock_dev_probe(struct platform_device *pdev)
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{
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struct q6afe_cc *cc;
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struct device *dev = &pdev->dev;
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int i, ret;
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cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
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if (!cc)
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return -ENOMEM;
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cc->clks = &q6afe_clks[0];
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cc->num_clks = ARRAY_SIZE(q6afe_clks);
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for (i = 0; i < ARRAY_SIZE(q6afe_clks); i++) {
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if (!q6afe_clks[i])
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continue;
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q6afe_clks[i]->dev = dev;
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ret = devm_clk_hw_register(dev, &q6afe_clks[i]->hw);
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if (ret)
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return ret;
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}
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ret = of_clk_add_hw_provider(dev->of_node, q6afe_of_clk_hw_get, cc);
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if (ret)
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return ret;
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dev_set_drvdata(dev, cc);
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return 0;
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}
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static const struct of_device_id q6afe_clock_device_id[] = {
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{ .compatible = "qcom,q6afe-clocks" },
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{},
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};
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MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
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static struct platform_driver q6afe_clock_platform_driver = {
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.driver = {
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.name = "q6afe-clock",
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.of_match_table = of_match_ptr(q6afe_clock_device_id),
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},
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.probe = q6afe_clock_dev_probe,
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};
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module_platform_driver(q6afe_clock_platform_driver);
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MODULE_DESCRIPTION("Q6 Audio Frontend clock driver");
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MODULE_LICENSE("GPL v2");
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