cxl/pci: Implement wait for media active
CXL 2.0 8.1.3.8.2 states: Memory_Active: When set, indicates that the CXL Range 1 memory is fully initialized and available for software use. Must be set within Range 1. Memory_Active_Timeout of deassertion of reset to CXL device if CXL.mem HwInit Mode=1 Unfortunately, Memory_Active can take quite a long time depending on media size (up to 256s per 2.0 spec). Provide a callback for the eventual establishment of CXL.mem operations via the 'cxl_mem' driver the 'struct cxl_memdev'. The implementation waits for 60s by default for now and can be overridden by the mbox_ready_time module parameter. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> [djbw: switch to sleeping wait] Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164298427373.3018233.9309741847039301834.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -132,6 +132,7 @@ struct cxl_endpoint_dvsec_info {
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* @component_reg_phys: register base of component registers
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* @info: Cached DVSEC information about the device.
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* @mbox_send: @dev specific transport for transmitting mailbox commands
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* @wait_media_ready: @dev specific method to await media ready
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*
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* See section 8.2.9.5.2 Capacity Configuration and Label Storage for
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* details on capacity parameters.
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@ -165,6 +166,7 @@ struct cxl_dev_state {
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struct cxl_endpoint_dvsec_info info;
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int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
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int (*wait_media_ready)(struct cxl_dev_state *cxlds);
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};
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enum cxl_opcode {
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@ -49,7 +49,7 @@
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static unsigned short mbox_ready_timeout = 60;
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module_param(mbox_ready_timeout, ushort, 0644);
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MODULE_PARM_DESC(mbox_ready_timeout,
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"seconds to wait for mailbox ready status");
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"seconds to wait for mailbox ready / memory active status");
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static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds)
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{
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@ -418,6 +418,51 @@ static int wait_for_valid(struct cxl_dev_state *cxlds)
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return -ETIMEDOUT;
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}
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/*
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* Wait up to @mbox_ready_timeout for the device to report memory
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* active.
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*/
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static int wait_for_media_ready(struct cxl_dev_state *cxlds)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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int d = cxlds->cxl_dvsec;
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bool active = false;
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u64 md_status;
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int rc, i;
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rc = wait_for_valid(cxlds);
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if (rc)
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return rc;
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for (i = mbox_ready_timeout; i; i--) {
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u32 temp;
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int rc;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &temp);
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if (rc)
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return rc;
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active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp);
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if (active)
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break;
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msleep(1000);
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}
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if (!active) {
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dev_err(&pdev->dev,
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"timeout awaiting memory active after %d seconds\n",
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mbox_ready_timeout);
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return -ETIMEDOUT;
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}
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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if (!CXLMDEV_READY(md_status))
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return -EIO;
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return 0;
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}
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static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
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{
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struct cxl_endpoint_dvsec_info *info = &cxlds->info;
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@ -528,6 +573,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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dev_warn(&pdev->dev,
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"Device DVSEC not present, skip CXL.mem init\n");
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cxlds->wait_media_ready = wait_for_media_ready;
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rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
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if (rc)
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return rc;
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@ -4,6 +4,7 @@
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <linux/bits.h>
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#include <cxlmem.h>
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@ -236,6 +237,12 @@ static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *
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return rc;
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}
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static int cxl_mock_wait_media_ready(struct cxl_dev_state *cxlds)
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{
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msleep(100);
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return 0;
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}
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static void label_area_release(void *lsa)
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{
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vfree(lsa);
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@ -262,6 +269,7 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
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return PTR_ERR(cxlds);
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cxlds->mbox_send = cxl_mock_mbox_send;
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cxlds->wait_media_ready = cxl_mock_wait_media_ready;
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cxlds->payload_size = SZ_4K;
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rc = cxl_enumerate_cmds(cxlds);
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