drm/amdgpu: support reserve bad page for virt (v3)
v1: rename some functions name, only init ras error handler data for
supported asic.
v2: fix potential memory leak.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Stanley.Yang
Alex Deucher
Родитель
6961750f12
Коммит
5278a159cf
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@ -2326,6 +2326,9 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
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{
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int i, r;
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if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
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amdgpu_virt_release_ras_err_handler_data(adev);
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amdgpu_ras_pre_fini(adev);
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if (adev->gmc.xgmi.num_physical_nodes > 1)
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@ -26,6 +26,7 @@
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#include <drm/drm_drv.h>
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
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{
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@ -255,12 +256,171 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj,
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return ret;
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}
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static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
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/* GPU will be marked bad on host if bp count more then 10,
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* so alloc 512 is enough.
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*/
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unsigned int align_space = 512;
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void *bps = NULL;
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struct amdgpu_bo **bps_bo = NULL;
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*data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
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if (!*data)
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return -ENOMEM;
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bps = kmalloc(align_space * sizeof((*data)->bps), GFP_KERNEL);
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bps_bo = kmalloc(align_space * sizeof((*data)->bps_bo), GFP_KERNEL);
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if (!bps || !bps_bo) {
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kfree(bps);
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kfree(bps_bo);
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kfree(*data);
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return -ENOMEM;
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}
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(*data)->bps = bps;
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(*data)->bps_bo = bps_bo;
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(*data)->count = 0;
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(*data)->last_reserved = 0;
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virt->ras_init_done = true;
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return 0;
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}
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static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
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struct amdgpu_bo *bo;
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int i;
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if (!data)
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return;
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for (i = data->last_reserved - 1; i >= 0; i--) {
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bo = data->bps_bo[i];
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amdgpu_bo_free_kernel(&bo, NULL, NULL);
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data->bps_bo[i] = bo;
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data->last_reserved = i;
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}
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}
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void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
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virt->ras_init_done = false;
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if (!data)
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return;
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amdgpu_virt_ras_release_bp(adev);
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kfree(data->bps);
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kfree(data->bps_bo);
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kfree(data);
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virt->virt_eh_data = NULL;
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}
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static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
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struct eeprom_table_record *bps, int pages)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
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if (!data)
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return;
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memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
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data->count += pages;
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}
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static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
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struct amdgpu_bo *bo = NULL;
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uint64_t bp;
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int i;
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if (!data)
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return;
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for (i = data->last_reserved; i < data->count; i++) {
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bp = data->bps[i].retired_page;
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/* There are two cases of reserve error should be ignored:
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* 1) a ras bad page has been allocated (used by someone);
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* 2) a ras bad page has been reserved (duplicate error injection
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* for one page);
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*/
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if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
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AMDGPU_GPU_PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&bo, NULL))
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DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
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data->bps_bo[i] = bo;
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data->last_reserved = i + 1;
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bo = NULL;
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}
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}
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static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
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uint64_t retired_page)
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{
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struct amdgpu_virt *virt = &adev->virt;
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struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
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int i;
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if (!data)
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return true;
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for (i = 0; i < data->count; i++)
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if (retired_page == data->bps[i].retired_page)
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return true;
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return false;
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}
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static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
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uint64_t bp_block_offset, uint32_t bp_block_size)
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{
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struct eeprom_table_record bp;
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uint64_t retired_page;
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uint32_t bp_idx, bp_cnt;
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if (bp_block_size) {
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bp_cnt = bp_block_size / sizeof(uint64_t);
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for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
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retired_page = *(uint64_t *)(adev->fw_vram_usage.va +
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bp_block_offset + bp_idx * sizeof(uint64_t));
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bp.retired_page = retired_page;
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if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
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continue;
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amdgpu_virt_ras_add_bps(adev, &bp, 1);
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amdgpu_virt_ras_reserve_bps(adev);
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}
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}
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}
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
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{
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uint32_t pf2vf_size = 0;
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uint32_t checksum = 0;
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uint32_t checkval;
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char *str;
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uint64_t bp_block_offset = 0;
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uint32_t bp_block_size = 0;
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struct amdgim_pf2vf_info_v2 *pf2vf_v2 = NULL;
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adev->virt.fw_reserve.p_pf2vf = NULL;
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adev->virt.fw_reserve.p_vf2pf = NULL;
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@ -275,6 +435,19 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
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/* pf2vf message must be in 4K */
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if (pf2vf_size > 0 && pf2vf_size < 4096) {
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if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
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pf2vf_v2 = (struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf;
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bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_L & 0xFFFFFFFF) |
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((((uint64_t)pf2vf_v2->bp_block_offset_H) << 32) & 0xFFFFFFFF00000000);
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bp_block_size = pf2vf_v2->bp_block_size;
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if (bp_block_size && !adev->virt.ras_init_done)
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amdgpu_virt_init_ras_err_handler_data(adev);
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if (adev->virt.ras_init_done)
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amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
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}
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checkval = amdgpu_virt_fw_reserve_get_checksum(
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adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
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adev->virt.fw_reserve.checksum_key, checksum);
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@ -143,19 +143,27 @@ struct amdgim_pf2vf_info_v2 {
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uint32_t vce_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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uint32_t vce_enc_max_bandwidth;
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/* Bad pages block position in BYTE */
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uint32_t bp_block_offset_L;
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uint32_t bp_block_offset_H;
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/* Bad pages block size in BYTE */
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uint32_t bp_block_size;
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/* MEC FW position in kb from the start of VF visible frame buffer */
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uint64_t mecfw_kboffset;
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uint32_t mecfw_kboffset_L;
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uint32_t mecfw_kboffset_H;
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/* MEC FW size in KB */
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uint32_t mecfw_ksize;
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/* UVD FW position in kb from the start of VF visible frame buffer */
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uint64_t uvdfw_kboffset;
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uint32_t uvdfw_kboffset_L;
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uint32_t uvdfw_kboffset_H;
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/* UVD FW size in KB */
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uint32_t uvdfw_ksize;
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/* VCE FW position in kb from the start of VF visible frame buffer */
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uint64_t vcefw_kboffset;
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uint32_t vcefw_kboffset_L;
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uint32_t vcefw_kboffset_H;
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/* VCE FW size in KB */
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uint32_t vcefw_ksize;
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uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)];
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uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
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} __aligned(4);
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@ -254,6 +262,17 @@ typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
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} \
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} while (0)
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struct amdgpu_virt_ras_err_handler_data {
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/* point to bad page records array */
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struct eeprom_table_record *bps;
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/* point to reserved bo array */
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struct amdgpu_bo **bps_bo;
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/* the count of entries */
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int count;
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/* last reserved entry's index + 1 */
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int last_reserved;
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};
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/* GPU virtualization */
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struct amdgpu_virt {
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uint32_t caps;
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@ -272,6 +291,8 @@ struct amdgpu_virt {
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uint32_t reg_access_mode;
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int req_init_data_ver;
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bool tdr_debug;
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struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
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bool ras_init_done;
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};
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#define amdgpu_sriov_enabled(adev) \
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@ -323,6 +344,7 @@ void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
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int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
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unsigned int key,
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unsigned int chksum);
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void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
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void amdgpu_detect_virtualization(struct amdgpu_device *adev);
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