i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Guennadi Liakhovetski
Dan Williams
Родитель
ef560682a9
Коммит
5296b56d1b
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@ -0,0 +1,181 @@
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/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IPU_H_
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#define _IPU_H_
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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/* IPU DMA Controller channel definitions. */
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enum ipu_channel {
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IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
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IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
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IDMAC_ADC_0 = 1,
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IDMAC_IC_2 = 2,
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IDMAC_ADC_1 = 2,
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IDMAC_IC_3 = 3,
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IDMAC_IC_4 = 4,
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IDMAC_IC_5 = 5,
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IDMAC_IC_6 = 6,
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IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
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IDMAC_IC_8 = 8,
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IDMAC_IC_9 = 9,
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IDMAC_IC_10 = 10,
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IDMAC_IC_11 = 11,
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IDMAC_IC_12 = 12,
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IDMAC_IC_13 = 13,
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IDMAC_SDC_0 = 14, /* Background synchronous display data */
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IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
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IDMAC_SDC_2 = 16,
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IDMAC_SDC_3 = 17,
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IDMAC_ADC_2 = 18,
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IDMAC_ADC_3 = 19,
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IDMAC_ADC_4 = 20,
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IDMAC_ADC_5 = 21,
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IDMAC_ADC_6 = 22,
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IDMAC_ADC_7 = 23,
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IDMAC_PF_0 = 24,
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IDMAC_PF_1 = 25,
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IDMAC_PF_2 = 26,
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IDMAC_PF_3 = 27,
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IDMAC_PF_4 = 28,
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IDMAC_PF_5 = 29,
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IDMAC_PF_6 = 30,
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IDMAC_PF_7 = 31,
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};
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/* Order significant! */
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enum ipu_channel_status {
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IPU_CHANNEL_FREE,
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IPU_CHANNEL_INITIALIZED,
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IPU_CHANNEL_READY,
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IPU_CHANNEL_ENABLED,
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};
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#define IPU_CHANNELS_NUM 32
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enum pixel_fmt {
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/* 1 byte */
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IPU_PIX_FMT_GENERIC,
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IPU_PIX_FMT_RGB332,
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IPU_PIX_FMT_YUV420P,
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IPU_PIX_FMT_YUV422P,
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IPU_PIX_FMT_YUV420P2,
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IPU_PIX_FMT_YVU422P,
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/* 2 bytes */
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IPU_PIX_FMT_RGB565,
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IPU_PIX_FMT_RGB666,
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IPU_PIX_FMT_BGR666,
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IPU_PIX_FMT_YUYV,
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IPU_PIX_FMT_UYVY,
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/* 3 bytes */
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IPU_PIX_FMT_RGB24,
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IPU_PIX_FMT_BGR24,
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/* 4 bytes */
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IPU_PIX_FMT_GENERIC_32,
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IPU_PIX_FMT_RGB32,
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IPU_PIX_FMT_BGR32,
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IPU_PIX_FMT_ABGR32,
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IPU_PIX_FMT_BGRA32,
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IPU_PIX_FMT_RGBA32,
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};
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enum ipu_color_space {
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IPU_COLORSPACE_RGB,
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IPU_COLORSPACE_YCBCR,
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IPU_COLORSPACE_YUV
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};
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/*
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* Enumeration of IPU rotation modes
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*/
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enum ipu_rotate_mode {
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/* Note the enum values correspond to BAM value */
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IPU_ROTATE_NONE = 0,
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IPU_ROTATE_VERT_FLIP = 1,
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IPU_ROTATE_HORIZ_FLIP = 2,
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IPU_ROTATE_180 = 3,
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IPU_ROTATE_90_RIGHT = 4,
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IPU_ROTATE_90_RIGHT_VFLIP = 5,
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IPU_ROTATE_90_RIGHT_HFLIP = 6,
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IPU_ROTATE_90_LEFT = 7,
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};
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struct ipu_platform_data {
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unsigned int irq_base;
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};
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/*
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* Enumeration of DI ports for ADC.
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*/
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enum display_port {
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DISP0,
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DISP1,
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DISP2,
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DISP3
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};
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struct idmac_video_param {
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unsigned short in_width;
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unsigned short in_height;
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uint32_t in_pixel_fmt;
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unsigned short out_width;
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unsigned short out_height;
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uint32_t out_pixel_fmt;
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unsigned short out_stride;
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bool graphics_combine_en;
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bool global_alpha_en;
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bool key_color_en;
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enum display_port disp;
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unsigned short out_left;
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unsigned short out_top;
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};
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/*
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* Union of initialization parameters for a logical channel. So far only video
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* parameters are used.
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*/
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union ipu_channel_param {
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struct idmac_video_param video;
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};
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struct idmac_tx_desc {
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struct dma_async_tx_descriptor txd;
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struct scatterlist *sg; /* scatterlist for this */
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unsigned int sg_len; /* tx-descriptor. */
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struct list_head list;
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};
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struct idmac_channel {
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struct dma_chan dma_chan;
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dma_cookie_t completed; /* last completed cookie */
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union ipu_channel_param params;
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enum ipu_channel link; /* input channel, linked to the output */
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enum ipu_channel_status status;
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void *client; /* Only one client per channel */
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unsigned int n_tx_desc;
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struct idmac_tx_desc *desc; /* allocated tx-descriptors */
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struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */
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struct list_head free_list; /* free tx-descriptors */
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struct list_head queue; /* queued tx-descriptors */
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spinlock_t lock; /* protects sg[0,1], queue */
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struct mutex chan_mutex; /* protects status, cookie, free_list */
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bool sec_chan_en;
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int active_buffer;
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unsigned int eof_irq;
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char eof_name[16]; /* EOF IRQ name for request_irq() */
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};
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#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
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#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
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#endif
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@ -35,7 +35,15 @@
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#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
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#define MXC_BOARD_IRQS 16
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#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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#ifdef CONFIG_MX3_IPU_IRQS
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#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
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#else
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#define MX3_IPU_IRQS 0
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#endif
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
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@ -62,6 +62,25 @@ config MV_XOR
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---help---
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Enable support for the Marvell XOR engine.
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config MX3_IPU
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bool "MX3x Image Processing Unit support"
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depends on ARCH_MX3
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select DMA_ENGINE
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default y
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help
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If you plan to use the Image Processing unit in the i.MX3x, say
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Y here. If unsure, select Y.
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config MX3_IPU_IRQS
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int "Number of dynamically mapped interrupts for IPU"
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depends on MX3_IPU
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range 2 137
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default 4
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help
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Out of 137 interrupt sources on i.MX31 IPU only very few are used.
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To avoid bloating the irq_desc[] array we allocate a sufficient
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number of IRQ slots and map them dynamically to specific sources.
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config DMA_ENGINE
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bool
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@ -7,3 +7,4 @@ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_MV_XOR) += mv_xor.o
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obj-$(CONFIG_DW_DMAC) += dw_dmac.o
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obj-$(CONFIG_MX3_IPU) += ipu/
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@ -0,0 +1 @@
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obj-y += ipu_irq.o ipu_idmac.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,176 @@
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/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IPU_INTERN_H_
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#define _IPU_INTERN_H_
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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/* IPU Common registers */
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#define IPU_CONF 0x00
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#define IPU_CHA_BUF0_RDY 0x04
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#define IPU_CHA_BUF1_RDY 0x08
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#define IPU_CHA_DB_MODE_SEL 0x0C
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#define IPU_CHA_CUR_BUF 0x10
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#define IPU_FS_PROC_FLOW 0x14
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#define IPU_FS_DISP_FLOW 0x18
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#define IPU_TASKS_STAT 0x1C
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#define IPU_IMA_ADDR 0x20
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#define IPU_IMA_DATA 0x24
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#define IPU_INT_CTRL_1 0x28
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#define IPU_INT_CTRL_2 0x2C
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#define IPU_INT_CTRL_3 0x30
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#define IPU_INT_CTRL_4 0x34
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#define IPU_INT_CTRL_5 0x38
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#define IPU_INT_STAT_1 0x3C
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#define IPU_INT_STAT_2 0x40
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#define IPU_INT_STAT_3 0x44
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#define IPU_INT_STAT_4 0x48
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#define IPU_INT_STAT_5 0x4C
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#define IPU_BRK_CTRL_1 0x50
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#define IPU_BRK_CTRL_2 0x54
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#define IPU_BRK_STAT 0x58
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#define IPU_DIAGB_CTRL 0x5C
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/* IPU_CONF Register bits */
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#define IPU_CONF_CSI_EN 0x00000001
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#define IPU_CONF_IC_EN 0x00000002
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#define IPU_CONF_ROT_EN 0x00000004
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#define IPU_CONF_PF_EN 0x00000008
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#define IPU_CONF_SDC_EN 0x00000010
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#define IPU_CONF_ADC_EN 0x00000020
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#define IPU_CONF_DI_EN 0x00000040
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#define IPU_CONF_DU_EN 0x00000080
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#define IPU_CONF_PXL_ENDIAN 0x00000100
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/* Image Converter Registers */
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#define IC_CONF 0x88
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#define IC_PRP_ENC_RSC 0x8C
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#define IC_PRP_VF_RSC 0x90
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#define IC_PP_RSC 0x94
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#define IC_CMBP_1 0x98
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#define IC_CMBP_2 0x9C
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#define PF_CONF 0xA0
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#define IDMAC_CONF 0xA4
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#define IDMAC_CHA_EN 0xA8
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#define IDMAC_CHA_PRI 0xAC
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#define IDMAC_CHA_BUSY 0xB0
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/* Image Converter Register bits */
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#define IC_CONF_PRPENC_EN 0x00000001
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#define IC_CONF_PRPENC_CSC1 0x00000002
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#define IC_CONF_PRPENC_ROT_EN 0x00000004
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#define IC_CONF_PRPVF_EN 0x00000100
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#define IC_CONF_PRPVF_CSC1 0x00000200
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#define IC_CONF_PRPVF_CSC2 0x00000400
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#define IC_CONF_PRPVF_CMB 0x00000800
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#define IC_CONF_PRPVF_ROT_EN 0x00001000
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#define IC_CONF_PP_EN 0x00010000
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#define IC_CONF_PP_CSC1 0x00020000
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#define IC_CONF_PP_CSC2 0x00040000
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#define IC_CONF_PP_CMB 0x00080000
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#define IC_CONF_PP_ROT_EN 0x00100000
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#define IC_CONF_IC_GLB_LOC_A 0x10000000
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#define IC_CONF_KEY_COLOR_EN 0x20000000
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#define IC_CONF_RWS_EN 0x40000000
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#define IC_CONF_CSI_MEM_WR_EN 0x80000000
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#define IDMA_CHAN_INVALID 0x000000FF
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#define IDMA_IC_0 0x00000001
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#define IDMA_IC_1 0x00000002
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#define IDMA_IC_2 0x00000004
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#define IDMA_IC_3 0x00000008
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#define IDMA_IC_4 0x00000010
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#define IDMA_IC_5 0x00000020
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#define IDMA_IC_6 0x00000040
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#define IDMA_IC_7 0x00000080
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#define IDMA_IC_8 0x00000100
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#define IDMA_IC_9 0x00000200
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#define IDMA_IC_10 0x00000400
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#define IDMA_IC_11 0x00000800
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#define IDMA_IC_12 0x00001000
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#define IDMA_IC_13 0x00002000
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#define IDMA_SDC_BG 0x00004000
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#define IDMA_SDC_FG 0x00008000
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#define IDMA_SDC_MASK 0x00010000
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#define IDMA_SDC_PARTIAL 0x00020000
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#define IDMA_ADC_SYS1_WR 0x00040000
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#define IDMA_ADC_SYS2_WR 0x00080000
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#define IDMA_ADC_SYS1_CMD 0x00100000
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#define IDMA_ADC_SYS2_CMD 0x00200000
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#define IDMA_ADC_SYS1_RD 0x00400000
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#define IDMA_ADC_SYS2_RD 0x00800000
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#define IDMA_PF_QP 0x01000000
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#define IDMA_PF_BSP 0x02000000
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#define IDMA_PF_Y_IN 0x04000000
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#define IDMA_PF_U_IN 0x08000000
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#define IDMA_PF_V_IN 0x10000000
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#define IDMA_PF_Y_OUT 0x20000000
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#define IDMA_PF_U_OUT 0x40000000
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#define IDMA_PF_V_OUT 0x80000000
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#define TSTAT_PF_H264_PAUSE 0x00000001
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#define TSTAT_CSI2MEM_MASK 0x0000000C
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#define TSTAT_CSI2MEM_OFFSET 2
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#define TSTAT_VF_MASK 0x00000600
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#define TSTAT_VF_OFFSET 9
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#define TSTAT_VF_ROT_MASK 0x000C0000
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#define TSTAT_VF_ROT_OFFSET 18
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#define TSTAT_ENC_MASK 0x00000180
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#define TSTAT_ENC_OFFSET 7
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#define TSTAT_ENC_ROT_MASK 0x00030000
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#define TSTAT_ENC_ROT_OFFSET 16
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#define TSTAT_PP_MASK 0x00001800
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#define TSTAT_PP_OFFSET 11
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#define TSTAT_PP_ROT_MASK 0x00300000
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#define TSTAT_PP_ROT_OFFSET 20
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#define TSTAT_PF_MASK 0x00C00000
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#define TSTAT_PF_OFFSET 22
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#define TSTAT_ADCSYS1_MASK 0x03000000
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#define TSTAT_ADCSYS1_OFFSET 24
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#define TSTAT_ADCSYS2_MASK 0x0C000000
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#define TSTAT_ADCSYS2_OFFSET 26
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#define TASK_STAT_IDLE 0
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#define TASK_STAT_ACTIVE 1
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#define TASK_STAT_WAIT4READY 2
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struct idmac {
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struct dma_device dma;
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};
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struct ipu {
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void __iomem *reg_ipu;
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void __iomem *reg_ic;
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unsigned int irq_fn; /* IPU Function IRQ to the CPU */
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unsigned int irq_err; /* IPU Error IRQ to the CPU */
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unsigned int irq_base; /* Beginning of the IPU IRQ range */
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unsigned long channel_init_mask;
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spinlock_t lock;
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struct clk *ipu_clk;
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struct device *dev;
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struct idmac idmac;
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struct idmac_channel channel[IPU_CHANNELS_NUM];
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struct tasklet_struct tasklet;
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};
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#define to_idmac(d) container_of(d, struct idmac, dma)
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extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
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extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
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extern bool ipu_irq_status(uint32_t irq);
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extern int ipu_irq_map(unsigned int source);
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extern int ipu_irq_unmap(unsigned int source);
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#endif
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@ -0,0 +1,413 @@
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/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/ipu.h>
|
||||
|
||||
#include "ipu_intern.h"
|
||||
|
||||
/*
|
||||
* Register read / write - shall be inlined by the compiler
|
||||
*/
|
||||
static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
|
||||
{
|
||||
return __raw_readl(ipu->reg_ipu + reg);
|
||||
}
|
||||
|
||||
static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
|
||||
{
|
||||
__raw_writel(value, ipu->reg_ipu + reg);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* IPU IRQ chip driver
|
||||
*/
|
||||
|
||||
#define IPU_IRQ_NR_FN_BANKS 3
|
||||
#define IPU_IRQ_NR_ERR_BANKS 2
|
||||
#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
|
||||
|
||||
struct ipu_irq_bank {
|
||||
unsigned int control;
|
||||
unsigned int status;
|
||||
spinlock_t lock;
|
||||
struct ipu *ipu;
|
||||
};
|
||||
|
||||
static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
|
||||
/* 3 groups of functional interrupts */
|
||||
{
|
||||
.control = IPU_INT_CTRL_1,
|
||||
.status = IPU_INT_STAT_1,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_2,
|
||||
.status = IPU_INT_STAT_2,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_3,
|
||||
.status = IPU_INT_STAT_3,
|
||||
},
|
||||
/* 2 groups of error interrupts */
|
||||
{
|
||||
.control = IPU_INT_CTRL_4,
|
||||
.status = IPU_INT_STAT_4,
|
||||
}, {
|
||||
.control = IPU_INT_CTRL_5,
|
||||
.status = IPU_INT_STAT_5,
|
||||
},
|
||||
};
|
||||
|
||||
struct ipu_irq_map {
|
||||
unsigned int irq;
|
||||
int source;
|
||||
struct ipu_irq_bank *bank;
|
||||
struct ipu *ipu;
|
||||
};
|
||||
|
||||
static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
|
||||
/* Protects allocations from the above array of maps */
|
||||
static DEFINE_MUTEX(map_lock);
|
||||
/* Protects register accesses and individual mappings */
|
||||
static DEFINE_SPINLOCK(bank_lock);
|
||||
|
||||
static struct ipu_irq_map *src2map(unsigned int src)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
|
||||
if (irq_map[i].source == src)
|
||||
return irq_map + i;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void ipu_irq_unmask(unsigned int irq)
|
||||
{
|
||||
struct ipu_irq_map *map = get_irq_chip_data(irq);
|
||||
struct ipu_irq_bank *bank;
|
||||
uint32_t reg;
|
||||
unsigned long lock_flags;
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
reg = ipu_read_reg(bank->ipu, bank->control);
|
||||
reg |= (1UL << (map->source & 31));
|
||||
ipu_write_reg(bank->ipu, reg, bank->control);
|
||||
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
static void ipu_irq_mask(unsigned int irq)
|
||||
{
|
||||
struct ipu_irq_map *map = get_irq_chip_data(irq);
|
||||
struct ipu_irq_bank *bank;
|
||||
uint32_t reg;
|
||||
unsigned long lock_flags;
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
reg = ipu_read_reg(bank->ipu, bank->control);
|
||||
reg &= ~(1UL << (map->source & 31));
|
||||
ipu_write_reg(bank->ipu, reg, bank->control);
|
||||
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
static void ipu_irq_ack(unsigned int irq)
|
||||
{
|
||||
struct ipu_irq_map *map = get_irq_chip_data(irq);
|
||||
struct ipu_irq_bank *bank;
|
||||
unsigned long lock_flags;
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
|
||||
bank = map->bank;
|
||||
if (!bank) {
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
pr_err("IPU: %s(%u) - unmapped!\n", __func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_status() - returns the current interrupt status of the specified IRQ.
|
||||
* @irq: interrupt line to get status for.
|
||||
* @return: true if the interrupt is pending/asserted or false if the
|
||||
* interrupt is not pending.
|
||||
*/
|
||||
bool ipu_irq_status(unsigned int irq)
|
||||
{
|
||||
struct ipu_irq_map *map = get_irq_chip_data(irq);
|
||||
struct ipu_irq_bank *bank;
|
||||
unsigned long lock_flags;
|
||||
bool ret;
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
bank = map->bank;
|
||||
ret = bank && ipu_read_reg(bank->ipu, bank->status) &
|
||||
(1UL << (map->source & 31));
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_map() - map an IPU interrupt source to an IRQ number
|
||||
* @source: interrupt source bit position (see below)
|
||||
* @return: mapped IRQ number or negative error code
|
||||
*
|
||||
* The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
|
||||
* sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
|
||||
* However, the source argument of this function is not the sequence number of
|
||||
* the possible IRQ, but rather its bit position. So, first interrupt in fourth
|
||||
* register has source number 96, and not 88. This makes calculations easier,
|
||||
* and also provides forward compatibility with any future IPU implementations
|
||||
* with any interrupt bit assignments.
|
||||
*/
|
||||
int ipu_irq_map(unsigned int source)
|
||||
{
|
||||
int i, ret = -ENOMEM;
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
might_sleep();
|
||||
|
||||
mutex_lock(&map_lock);
|
||||
map = src2map(source);
|
||||
if (map) {
|
||||
pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
if (irq_map[i].source < 0) {
|
||||
unsigned long lock_flags;
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
irq_map[i].source = source;
|
||||
irq_map[i].bank = irq_bank + source / 32;
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
ret = irq_map[i].irq;
|
||||
pr_debug("IPU: mapped source %u to IRQ %u\n",
|
||||
source, ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&map_lock);
|
||||
|
||||
if (ret < 0)
|
||||
pr_err("IPU: couldn't map source %u: %d\n", source, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu_irq_map() - map an IPU interrupt source to an IRQ number
|
||||
* @source: interrupt source bit position (see ipu_irq_map())
|
||||
* @return: 0 or negative error code
|
||||
*/
|
||||
int ipu_irq_unmap(unsigned int source)
|
||||
{
|
||||
int i, ret = -EINVAL;
|
||||
|
||||
might_sleep();
|
||||
|
||||
mutex_lock(&map_lock);
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
if (irq_map[i].source == source) {
|
||||
unsigned long lock_flags;
|
||||
|
||||
pr_debug("IPU: unmapped source %u from IRQ %u\n",
|
||||
source, irq_map[i].irq);
|
||||
|
||||
spin_lock_irqsave(&bank_lock, lock_flags);
|
||||
irq_map[i].source = -EINVAL;
|
||||
irq_map[i].bank = NULL;
|
||||
spin_unlock_irqrestore(&bank_lock, lock_flags);
|
||||
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&map_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Chained IRQ handler for IPU error interrupt */
|
||||
static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct ipu *ipu = get_irq_data(irq);
|
||||
u32 status;
|
||||
int i, line;
|
||||
|
||||
for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
|
||||
struct ipu_irq_bank *bank = irq_bank + i;
|
||||
|
||||
spin_lock(&bank_lock);
|
||||
status = ipu_read_reg(ipu, bank->status);
|
||||
/*
|
||||
* Don't think we have to clear all interrupts here, they will
|
||||
* be acked by ->handle_irq() (handle_level_irq). However, we
|
||||
* might want to clear unhandled interrupts after the loop...
|
||||
*/
|
||||
status &= ipu_read_reg(ipu, bank->control);
|
||||
spin_unlock(&bank_lock);
|
||||
while ((line = ffs(status))) {
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
line--;
|
||||
status &= ~(1UL << line);
|
||||
|
||||
spin_lock(&bank_lock);
|
||||
map = src2map(32 * i + line);
|
||||
if (map)
|
||||
irq = map->irq;
|
||||
spin_unlock(&bank_lock);
|
||||
|
||||
if (!map) {
|
||||
pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
|
||||
line, i);
|
||||
continue;
|
||||
}
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Chained IRQ handler for IPU function interrupt */
|
||||
static void ipu_irq_fn(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct ipu *ipu = get_irq_data(irq);
|
||||
u32 status;
|
||||
int i, line;
|
||||
|
||||
for (i = 0; i < IPU_IRQ_NR_FN_BANKS; i++) {
|
||||
struct ipu_irq_bank *bank = irq_bank + i;
|
||||
|
||||
spin_lock(&bank_lock);
|
||||
status = ipu_read_reg(ipu, bank->status);
|
||||
/* Not clearing all interrupts, see above */
|
||||
status &= ipu_read_reg(ipu, bank->control);
|
||||
spin_unlock(&bank_lock);
|
||||
while ((line = ffs(status))) {
|
||||
struct ipu_irq_map *map;
|
||||
|
||||
line--;
|
||||
status &= ~(1UL << line);
|
||||
|
||||
spin_lock(&bank_lock);
|
||||
map = src2map(32 * i + line);
|
||||
if (map)
|
||||
irq = map->irq;
|
||||
spin_unlock(&bank_lock);
|
||||
|
||||
if (!map) {
|
||||
pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
|
||||
line, i);
|
||||
continue;
|
||||
}
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip ipu_irq_chip = {
|
||||
.name = "ipu_irq",
|
||||
.ack = ipu_irq_ack,
|
||||
.mask = ipu_irq_mask,
|
||||
.unmask = ipu_irq_unmask,
|
||||
};
|
||||
|
||||
/* Install the IRQ handler */
|
||||
int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
{
|
||||
struct ipu_platform_data *pdata = dev->dev.platform_data;
|
||||
unsigned int irq, irq_base, i;
|
||||
|
||||
irq_base = pdata->irq_base;
|
||||
|
||||
for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
|
||||
irq_bank[i].ipu = ipu;
|
||||
|
||||
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
|
||||
int ret;
|
||||
|
||||
irq = irq_base + i;
|
||||
ret = set_irq_chip(irq, &ipu_irq_chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = set_irq_chip_data(irq, irq_map + i);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
irq_map[i].ipu = ipu;
|
||||
irq_map[i].irq = irq;
|
||||
irq_map[i].source = -EINVAL;
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
#ifdef CONFIG_ARM
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
#endif
|
||||
}
|
||||
|
||||
set_irq_data(ipu->irq_fn, ipu);
|
||||
set_irq_chained_handler(ipu->irq_fn, ipu_irq_fn);
|
||||
|
||||
set_irq_data(ipu->irq_err, ipu);
|
||||
set_irq_chained_handler(ipu->irq_err, ipu_irq_err);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
{
|
||||
struct ipu_platform_data *pdata = dev->dev.platform_data;
|
||||
unsigned int irq, irq_base;
|
||||
|
||||
irq_base = pdata->irq_base;
|
||||
|
||||
set_irq_chained_handler(ipu->irq_fn, NULL);
|
||||
set_irq_data(ipu->irq_fn, NULL);
|
||||
|
||||
set_irq_chained_handler(ipu->irq_err, NULL);
|
||||
set_irq_data(ipu->irq_err, NULL);
|
||||
|
||||
for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
|
||||
#ifdef CONFIG_ARM
|
||||
set_irq_flags(irq, 0);
|
||||
#endif
|
||||
set_irq_chip(irq, NULL);
|
||||
set_irq_chip_data(irq, NULL);
|
||||
}
|
||||
}
|
||||
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