Big fix for IDT NTB and Intel NTB LTR management support
-----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEoE9b9c3U2JxX98mqbmZLrHqL0iMFAl/oloUACgkQbmZLrHqL 0iOnHBAAlQmxy/OBQSeOVT4mZh954zUwUl8CTpOLraMgNh/aUGK48MxGgDNQ0k77 WFtoKKGqdeAAyVyQmnirtWi811tbCt+wl07jorOuO79AXvx11IQEI2qA2udoexlO xrI/7UukVWWeOvRuP6Nbi2iJvzkuJ7h9hgyHqloBj63PNh5PSJb1u8T+48yyVvvM LftGsIW6FOc1Dl6ZHBnezd6mNjqsBJMyggkD2BR/QOwEAJI7mWI4ihU6fZSzSoAv o69V/SVMAiDzUWsFlzvOIPfNgQ4pw7HbIyS80sj4oFGL5meiuH7L7RrtMLVOKvIm fYmhqt+1F36NiRGIPibPjD9tgt1jCXFfh/R4ZuLldJ/vjVZxP4Bqoyhvbntum8o5 quKq5zO/Ou1b/9f9uBzJ31/EnOqVg3nNx/i09t5KH1Knp0kfLMTPgEtdyRZbm2+V oQ+iCUiO5FTbWZhW+/CgM59HRSM3LtXCRateMEcSkQxEa6smCKAL4BuV9tIRN93g MotqKfSmvOovQC/tixxAI2SxwmdovtssrELxcvbsiqjlh3PAmp1IhA9q/yPW2g4/ vzK+2cYLWDovdERCGPo4i+Eb838nufEXhf0OEQowkwM66V86sdCRUJLFPUJdw7l5 3XgNWC086TXpKSP9URnRUnRPhDecdwmVotWxfXBewiNYZyY1AQE= =dBeS -----END PGP SIGNATURE----- Merge tag 'ntb-5.11' of git://github.com/jonmason/ntb Pull NTB fixes from Jon Mason: "Bug fix for IDT NTB and Intel NTB LTR management support" * tag 'ntb-5.11' of git://github.com/jonmason/ntb: ntb: intel: add Intel NTB LTR vendor support for gen4 NTB ntb: idt: fix error check in ntb_hw_idt.c
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52cd5f9c22
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@ -2511,7 +2511,7 @@ static int idt_init_dbgfs(struct idt_ntb_dev *ndev)
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/* If the top directory is not created then do nothing */
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if (IS_ERR_OR_NULL(dbgfs_topdir)) {
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dev_info(&ndev->ntb.pdev->dev, "Top DebugFS directory absent");
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return PTR_ERR(dbgfs_topdir);
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return PTR_ERR_OR_ZERO(dbgfs_topdir);
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}
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/* Create the info file node */
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@ -2756,7 +2756,7 @@ static int idt_pci_probe(struct pci_dev *pdev,
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/* Allocate the memory for IDT NTB device data */
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ndev = idt_create_dev(pdev, id);
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if (IS_ERR_OR_NULL(ndev))
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if (IS_ERR(ndev))
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return PTR_ERR(ndev);
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/* Initialize the basic PCI subsystem of the device */
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@ -141,6 +141,7 @@
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#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
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#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
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#define NTB_HWERR_BAR_ALIGN BIT_ULL(4)
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#define NTB_HWERR_LTR_BAD BIT_ULL(5)
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extern struct intel_b2b_addr xeon_b2b_usd_addr;
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extern struct intel_b2b_addr xeon_b2b_dsd_addr;
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@ -177,8 +177,10 @@ int gen4_init_dev(struct intel_ntb_dev *ndev)
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ndev->reg = &gen4_reg;
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if (pdev_is_ICX(pdev))
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if (pdev_is_ICX(pdev)) {
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ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;
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ndev->hwerr_flags |= NTB_HWERR_LTR_BAD;
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}
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ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
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ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
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@ -431,6 +433,25 @@ static int intel_ntb4_link_enable(struct ntb_dev *ntb,
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dev_dbg(&ntb->pdev->dev,
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"ignoring max_width %d\n", max_width);
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if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) {
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u32 ltr;
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/* Setup active snoop LTR values */
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ltr = NTB_LTR_ACTIVE_REQMNT | NTB_LTR_ACTIVE_VAL | NTB_LTR_ACTIVE_LATSCALE;
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/* Setup active non-snoop values */
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ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
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iowrite32(ltr, ndev->self_mmio + GEN4_LTR_ACTIVE_OFFSET);
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/* Setup idle snoop LTR values */
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ltr = NTB_LTR_IDLE_VAL | NTB_LTR_IDLE_LATSCALE | NTB_LTR_IDLE_REQMNT;
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/* Setup idle non-snoop values */
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ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
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iowrite32(ltr, ndev->self_mmio + GEN4_LTR_IDLE_OFFSET);
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/* setup PCIe LTR to active */
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iowrite8(NTB_LTR_SWSEL_ACTIVE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
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}
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ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP;
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ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP;
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iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
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@ -476,6 +497,10 @@ static int intel_ntb4_link_disable(struct ntb_dev *ntb)
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lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
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iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
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/* set LTR to idle */
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if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD))
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iowrite8(NTB_LTR_SWSEL_IDLE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
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ndev->dev_up = 0;
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return 0;
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@ -35,6 +35,9 @@
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#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */
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#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */
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#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */
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#define GEN4_LTR_SWSEL_OFFSET 0x30ec
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#define GEN4_LTR_ACTIVE_OFFSET 0x30f0
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#define GEN4_LTR_IDLE_OFFSET 0x30f4
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#define GEN4_EM_SPAD_OFFSET 0x8080
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/* note, link status is now in MMIO and not config space for NTB */
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#define GEN4_LINK_CTRL_OFFSET 0xb050
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@ -80,6 +83,18 @@
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#define NTB_SJC_FORCEDETECT 0x000004
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#define NTB_LTR_SWSEL_ACTIVE 0x0
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#define NTB_LTR_SWSEL_IDLE 0x1
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#define NTB_LTR_NS_SHIFT 16
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#define NTB_LTR_ACTIVE_VAL 0x0000 /* 0 us */
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#define NTB_LTR_ACTIVE_LATSCALE 0x0800 /* 1us scale */
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#define NTB_LTR_ACTIVE_REQMNT 0x8000 /* snoop req enable */
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#define NTB_LTR_IDLE_VAL 0x0258 /* 600 us */
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#define NTB_LTR_IDLE_LATSCALE 0x0800 /* 1us scale */
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#define NTB_LTR_IDLE_REQMNT 0x8000 /* snoop req enable */
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ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
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size_t count, loff_t *offp);
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int gen4_init_dev(struct intel_ntb_dev *ndev);
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