Staging: vme: Assure D16 cycle if required in master_read and master_write
From a95892fc2246d6dc45f57b7dd68f32b9b28bd0f7 Mon Sep 17 00:00:00 2001 From: Arthur Benilov <arthur.benilov@gmail.com> Date: Fri, 24 Sep 2010 13:51:07 +0200 Subject: [PATCH] Staging: vme: Assure D16 cycle if required in master_read and master_write memcpy_fromio() and memcpy_toio() functions apply internally to __memcpy() that performs data transfer in 32-bits or 8-bits blocks (at least on x86). This makes impossible to perform D16 cycle with ca91cx42 bridge. Provided modification assures performing data transfer with 32, 16, and 8 bits chunks. Signed-off-by: Arthur Benilov <arthur.benilov@iba-group.com> Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Родитель
0abd242839
Коммит
53059aa059
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@ -848,12 +848,57 @@ ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
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size_t count, loff_t offset)
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{
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ssize_t retval;
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void *addr = image->kern_base + offset;
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unsigned int done = 0;
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unsigned int count32;
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if (count == 0)
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return 0;
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spin_lock(&(image->lock));
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memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
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retval = count;
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/* The following code handles VME address alignment problem
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* in order to assure the maximal data width cycle.
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* We cannot use memcpy_xxx directly here because it
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* may cut data transfer in 8-bits cycles, thus making
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* D16 cycle impossible.
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* From the other hand, the bridge itself assures that
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* maximal configured data cycle is used and splits it
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* automatically for non-aligned addresses.
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*/
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if ((int)addr & 0x1) {
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*(u8 *)buf = ioread8(addr);
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done += 1;
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if (done == count)
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goto out;
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}
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if ((int)addr & 0x2) {
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if ((count - done) < 2) {
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*(u8 *)(buf + done) = ioread8(addr + done);
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done += 1;
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goto out;
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} else {
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*(u16 *)(buf + done) = ioread16(addr + done);
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done += 2;
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}
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}
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count32 = (count - done) & ~0x3;
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if (count32 > 0) {
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memcpy_fromio(buf + done, addr + done, (unsigned int)count);
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done += count32;
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}
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if ((count - done) & 0x2) {
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*(u16 *)(buf + done) = ioread16(addr + done);
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done += 2;
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}
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if ((count - done) & 0x1) {
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*(u8 *)(buf + done) = ioread8(addr + done);
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done += 1;
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}
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out:
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retval = count;
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spin_unlock(&(image->lock));
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return retval;
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@ -862,15 +907,54 @@ ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
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ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
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size_t count, loff_t offset)
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{
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int retval = 0;
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ssize_t retval;
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void *addr = image->kern_base + offset;
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unsigned int done = 0;
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unsigned int count32;
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if (count == 0)
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return 0;
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spin_lock(&(image->lock));
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memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
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/* Here we apply for the same strategy we do in master_read
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* function in order to assure D16 cycle when required.
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*/
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if ((int)addr & 0x1) {
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iowrite8(*(u8 *)buf, addr);
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done += 1;
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if (done == count)
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goto out;
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}
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if ((int)addr & 0x2) {
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if ((count - done) < 2) {
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iowrite8(*(u8 *)(buf + done), addr + done);
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done += 1;
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goto out;
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} else {
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iowrite16(*(u16 *)(buf + done), addr + done);
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done += 2;
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}
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}
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count32 = (count - done) & ~0x3;
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if (count32 > 0) {
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memcpy_toio(addr + done, buf + done, count32);
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done += count32;
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}
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if ((count - done) & 0x2) {
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iowrite16(*(u16 *)(buf + done), addr + done);
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done += 2;
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}
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if ((count - done) & 0x1) {
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iowrite8(*(u8 *)(buf + done), addr + done);
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done += 1;
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}
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out:
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retval = count;
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spin_unlock(&(image->lock));
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return retval;
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}
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