i7core_edac: scrubbing fixups
Get a more reliable DCLK value from DMI, name the SCRUBINTERVAL mask and guard against potential overflow in the scrub rate computations. Signed-off-by: Nils Carlson <nils.carlson@ericsson.com>
This commit is contained in:
Nils Carlson
Mauro Carvalho Chehab
Родитель
168eb34ded
Коммит
535e9c78e1
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@ -31,6 +31,7 @@
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/edac.h>
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#include <linux/mmzone.h>
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#include <linux/smp.h>
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@ -107,6 +108,7 @@ MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
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#define MC_SCRUB_CONTROL 0x4c
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#define STARTSCRUB (1 << 24)
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#define SCRUBINTERVAL_MASK 0xffffff
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#define MC_COR_ECC_CNT_0 0x80
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#define MC_COR_ECC_CNT_1 0x84
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@ -275,6 +277,9 @@ struct i7core_pvt {
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/* Count indicator to show errors not got */
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unsigned mce_overrun;
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/* DCLK Frequency used for computing scrub rate */
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int dclk_freq;
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/* Struct to control EDAC polling */
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struct edac_pci_ctl_info *i7core_pci;
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};
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@ -1952,6 +1957,112 @@ static struct notifier_block i7_mce_dec = {
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.notifier_call = i7core_mce_check_error,
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};
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struct memdev_dmi_entry {
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u8 type;
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u8 length;
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u16 handle;
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u16 phys_mem_array_handle;
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u16 mem_err_info_handle;
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u16 total_width;
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u16 data_width;
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u16 size;
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u8 form;
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u8 device_set;
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u8 device_locator;
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u8 bank_locator;
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u8 memory_type;
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u16 type_detail;
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u16 speed;
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u8 manufacturer;
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u8 serial_number;
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u8 asset_tag;
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u8 part_number;
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u8 attributes;
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u32 extended_size;
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u16 conf_mem_clk_speed;
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} __attribute__((__packed__));
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/*
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* Decode the DRAM Clock Frequency, be paranoid, make sure that all
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* memory devices show the same speed, and if they don't then consider
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* all speeds to be invalid.
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*/
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static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
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{
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int *dclk_freq = _dclk_freq;
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u16 dmi_mem_clk_speed;
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if (*dclk_freq == -1)
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return;
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if (dh->type == DMI_ENTRY_MEM_DEVICE) {
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struct memdev_dmi_entry *memdev_dmi_entry =
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(struct memdev_dmi_entry *)dh;
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unsigned long conf_mem_clk_speed_offset =
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(unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
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(unsigned long)&memdev_dmi_entry->type;
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unsigned long speed_offset =
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(unsigned long)&memdev_dmi_entry->speed -
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(unsigned long)&memdev_dmi_entry->type;
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/* Check that a DIMM is present */
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if (memdev_dmi_entry->size == 0)
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return;
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/*
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* Pick the configured speed if it's available, otherwise
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* pick the DIMM speed, or we don't have a speed.
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*/
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if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
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dmi_mem_clk_speed =
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memdev_dmi_entry->conf_mem_clk_speed;
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} else if (memdev_dmi_entry->length > speed_offset) {
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dmi_mem_clk_speed = memdev_dmi_entry->speed;
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} else {
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*dclk_freq = -1;
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return;
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}
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if (*dclk_freq == 0) {
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/* First pass, speed was 0 */
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if (dmi_mem_clk_speed > 0) {
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/* Set speed if a valid speed is read */
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*dclk_freq = dmi_mem_clk_speed;
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} else {
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/* Otherwise we don't have a valid speed */
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*dclk_freq = -1;
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}
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} else if (*dclk_freq > 0 &&
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*dclk_freq != dmi_mem_clk_speed) {
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/*
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* If we have a speed, check that all DIMMS are the same
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* speed, otherwise set the speed as invalid.
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*/
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*dclk_freq = -1;
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}
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}
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}
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/*
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* The default DCLK frequency is used as a fallback if we
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* fail to find anything reliable in the DMI. The value
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* is taken straight from the datasheet.
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*/
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#define DEFAULT_DCLK_FREQ 800
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static int get_dclk_freq(void)
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{
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int dclk_freq = 0;
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dmi_walk(decode_dclk, (void *)&dclk_freq);
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if (dclk_freq < 1)
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return DEFAULT_DCLK_FREQ;
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return dclk_freq;
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}
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/*
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* set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
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* to hardware according to SCRUBINTERVAL formula
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@ -1961,8 +2072,6 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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struct pci_dev *pdev;
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const u32 cache_line_size = 64;
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const u32 freq_dclk = 800*1000000;
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u32 dw_scrub;
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u32 dw_ssr;
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@ -1977,18 +2086,28 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
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/* Prepare to disable petrol scrub */
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dw_scrub &= ~STARTSCRUB;
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/* Stop the patrol scrub engine */
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write_and_test(pdev, MC_SCRUB_CONTROL, dw_scrub & ~0x00ffffff);
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write_and_test(pdev, MC_SCRUB_CONTROL,
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dw_scrub & ~SCRUBINTERVAL_MASK);
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/* Get current status of scrub rate and set bit to disable */
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pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
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dw_ssr &= ~SSR_MODE_MASK;
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dw_ssr |= SSR_MODE_DISABLE;
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} else {
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const int cache_line_size = 64;
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const u32 freq_dclk_mhz = pvt->dclk_freq;
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unsigned long long scrub_interval;
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/*
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* Translate the desired scrub rate to a register value and
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* program the cooresponding register value.
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* program the corresponding register value.
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*/
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dw_scrub = 0x00ffffff & (cache_line_size * freq_dclk / new_bw);
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scrub_interval = (unsigned long long)freq_dclk_mhz *
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cache_line_size * 1000000 / new_bw;
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if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
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return -EINVAL;
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dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
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/* Start the patrol scrub engine */
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pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
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@ -2015,7 +2134,8 @@ static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
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struct i7core_pvt *pvt = mci->pvt_info;
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struct pci_dev *pdev;
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const u32 cache_line_size = 64;
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const u32 freq_dclk = 800*1000000;
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const u32 freq_dclk_mhz = pvt->dclk_freq;
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unsigned long long scrub_rate;
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u32 scrubval;
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/* Get data from the MC register, function 2 */
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@ -2027,12 +2147,14 @@ static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
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pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
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/* Mask highest 8-bits to 0 */
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scrubval &= 0x00ffffff;
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scrubval &= SCRUBINTERVAL_MASK;
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if (!scrubval)
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return 0;
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/* Calculate scrub rate value into byte/sec bandwidth */
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return 0xffffffff & (cache_line_size * freq_dclk / (u64) scrubval);
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scrub_rate = (unsigned long long)freq_dclk_mhz *
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1000000 * cache_line_size / scrubval;
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return (int)scrub_rate;
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}
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static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
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@ -2204,6 +2326,9 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev)
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/* allocating generic PCI control info */
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i7core_pci_ctl_create(pvt);
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/* DCLK for scrub rate setting */
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pvt->dclk_freq = get_dclk_freq();
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atomic_notifier_chain_register(&x86_mce_decoder_chain, &i7_mce_dec);
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return 0;
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