pinctrl: sh-pfc: Updates for v4.8
- Voltage switching support for R-Car H3, - DRIF pin support for R-Car H3, - Cleanups and fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXa+TyAAoJEEgEtLw/Ve77RmMP/0mKf4GRXg0WtgNAUrWcHxNh 4BmGaMNBRpRDSRwLUhlQn+JJd2+6hKWs1frJgg9xKCxNgKeU0AhNraOoPxjpq7s2 oPPlioDWJgIlda5z+eigQmNjJs7qgncQqGctOJcz8r8WQLOXaMsF95bFT3236iNa xYWdRJRAT6/h/5gkAbaA7VFXy0a3Yl0e2eMFrHAaTiUI2OHszh6a/gyREV1gKOiP 8tPs9+098Yq8UH/99/S5MEnjo4nRq4qwdLE2nmoEnutT5LneBdXtgJkP7JUBvxUO yJuHR8o5HldQv2I4yBs8JZQ7sFW94wHyRN7hl05WaL0lMpnj/i03X/hwMP9Vopaz cXl0fLMzpGUWDVdl7LoVhDpTnWT2vFYkydgIIVv2KJtJ3HByby56D1BiApBfCOPc Z/NFm0siU30vDYPv1A1Pr4DUChJDQ1CH9SiMJtTQmO9I51xdKGOCnka6R8b4Ym0D DWy0jKUuVUK299NBDn86+Cal96HTNYj1ehdBdGazAve2MESw+Pve+ML9MtlLPsdw xjoegoQGVrONMx7E8FVcLtDs7lah0LZAaw0I/WKs1PDHIeHsBuLNJJW0dsjjEEyq 0KQ5XcY23gmiqmXiYMuUyfYRt++YhhIN81VZBp49jePOyN9N3PH7hKEO24Btku26 NRyXH4L/VedVL5eCDf4H =z1/q -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.8 - Voltage switching support for R-Car H3, - DRIF pin support for R-Car H3, - Cleanups and fixes.
This commit is contained in:
Linus Walleij
Коммит
53673a5179
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@ -72,7 +72,7 @@ Pin Configuration Node Properties:
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The pin configuration parameters use the generic pinconf bindings defined in
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pinctrl-bindings.txt in this directory. The supported parameters are
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bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For
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bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
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pins that have a configurable I/O voltage, the power-source value should be the
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nominal I/O voltage in millivolts.
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@ -598,15 +598,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
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return 0;
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}
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static int sh_pfc_remove(struct platform_device *pdev)
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{
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#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
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sh_pfc_unregister_gpiochip(platform_get_drvdata(pdev));
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#endif
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return 0;
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}
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static const struct platform_device_id sh_pfc_id_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_SH7203
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{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
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@ -650,7 +641,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
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static struct platform_driver sh_pfc_driver = {
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.probe = sh_pfc_probe,
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.remove = sh_pfc_remove,
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.id_table = sh_pfc_id_table,
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.driver = {
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.name = DRV_NAME,
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@ -10,50 +10,16 @@
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#ifndef __SH_PFC_CORE_H__
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#define __SH_PFC_CORE_H__
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "sh_pfc.h"
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struct sh_pfc_window {
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phys_addr_t phys;
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void __iomem *virt;
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unsigned long size;
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};
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struct sh_pfc_chip;
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struct sh_pfc_pinctrl;
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struct sh_pfc_pin_range {
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u16 start;
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u16 end;
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};
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struct sh_pfc {
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struct device *dev;
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const struct sh_pfc_soc_info *info;
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spinlock_t lock;
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unsigned int num_windows;
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struct sh_pfc_window *windows;
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unsigned int num_irqs;
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unsigned int *irqs;
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struct sh_pfc_pin_range *ranges;
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unsigned int nr_ranges;
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unsigned int nr_gpio_pins;
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struct sh_pfc_chip *gpio;
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#ifdef CONFIG_SUPERH
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struct sh_pfc_chip *func;
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#endif
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};
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int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
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int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
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@ -67,28 +33,4 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
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extern const struct sh_pfc_soc_info emev2_pinmux_info;
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extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info sh7203_pinmux_info;
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extern const struct sh_pfc_soc_info sh7264_pinmux_info;
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extern const struct sh_pfc_soc_info sh7269_pinmux_info;
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extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
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extern const struct sh_pfc_soc_info sh7720_pinmux_info;
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extern const struct sh_pfc_soc_info sh7722_pinmux_info;
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extern const struct sh_pfc_soc_info sh7723_pinmux_info;
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extern const struct sh_pfc_soc_info sh7724_pinmux_info;
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extern const struct sh_pfc_soc_info sh7734_pinmux_info;
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extern const struct sh_pfc_soc_info sh7757_pinmux_info;
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extern const struct sh_pfc_soc_info sh7785_pinmux_info;
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extern const struct sh_pfc_soc_info sh7786_pinmux_info;
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extern const struct sh_pfc_soc_info shx3_pinmux_info;
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#endif /* __SH_PFC_CORE_H__ */
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@ -318,7 +318,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
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if (ret < 0)
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return ERR_PTR(ret);
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ret = gpiochip_add_data(&chip->gpio_chip, chip);
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ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
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if (unlikely(ret < 0))
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return ERR_PTR(ret);
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@ -399,18 +399,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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pfc->func = chip;
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#endif /* CONFIG_SUPERH */
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return 0;
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}
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int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
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{
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gpiochip_remove(&pfc->gpio->gpio_chip);
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#ifdef CONFIG_SUPERH
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gpiochip_remove(&pfc->func->gpio_chip);
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#endif
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return 0;
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}
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@ -21,7 +21,6 @@
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, pfx, sfx) \
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@ -22,7 +22,6 @@
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, pfx, sfx) \
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@ -23,7 +23,7 @@
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
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@ -24,7 +24,6 @@
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include "core.h"
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#include "sh_pfc.h"
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/*
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@ -4696,47 +4695,6 @@ static const char * const vin3_groups[] = {
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"vin3_clk",
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};
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#define IOCTRL6 0x8c
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static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin)
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{
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u32 data, mask;
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if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
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return -EINVAL;
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data = ioread32(pfc->windows->virt + IOCTRL6),
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/* Bits in IOCTRL6 are numbered in opposite order to pins */
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mask = 0x80000000 >> (pin & 0x1f);
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return (data & mask) ? 3300 : 1800;
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}
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static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV)
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{
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u32 data, mask;
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if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
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return -EINVAL;
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if (mV != 1800 && mV != 3300)
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return -EINVAL;
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data = ioread32(pfc->windows->virt + IOCTRL6);
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/* Bits in IOCTRL6 are numbered in opposite order to pins */
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mask = 0x80000000 >> (pin & 0x1f);
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if (mV == 3300)
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data |= mask;
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else
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data &= ~mask;
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iowrite32(~data, pfc->windows->virt); /* unlock reg */
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iowrite32(data, pfc->windows->virt + IOCTRL6);
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return 0;
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}
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(audio_clk),
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SH_PFC_FUNCTION(avb),
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@ -5736,14 +5694,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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static const struct sh_pfc_soc_operations pinmux_ops = {
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.get_io_voltage = r8a7790_get_io_voltage,
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.set_io_voltage = r8a7790_set_io_voltage,
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static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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{
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if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
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return -EINVAL;
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*pocctrl = 0xe606008c;
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return 31 - (pin & 0x1f);
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}
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static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
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.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
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};
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const struct sh_pfc_soc_info r8a7790_pinmux_info = {
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.name = "r8a77900_pfc",
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.ops = &pinmux_ops,
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.ops = &r8a7790_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@ -11,7 +11,6 @@
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#include <linux/kernel.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, sfx) \
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@ -17,8 +17,12 @@
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PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_16(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
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@ -552,6 +556,9 @@ static const u16 pinmux_data[] = {
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PINMUX_SINGLE(AVS2),
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PINMUX_SINGLE(HDMI0_CEC),
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PINMUX_SINGLE(HDMI1_CEC),
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PINMUX_SINGLE(I2C_SEL_0_1),
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PINMUX_SINGLE(I2C_SEL_3_1),
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PINMUX_SINGLE(I2C_SEL_5_1),
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PINMUX_SINGLE(MSIOF0_RXD),
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PINMUX_SINGLE(MSIOF0_SCK),
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PINMUX_SINGLE(MSIOF0_TXD),
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@ -1401,11 +1408,6 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
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PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
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PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
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/* I2C */
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PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
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PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
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PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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@ -1654,6 +1656,221 @@ static const unsigned int canfd1_data_mux[] = {
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CANFD1_TX_MARK, CANFD1_RX_MARK,
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};
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/* - DRIF0 --------------------------------------------------------------- */
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static const unsigned int drif0_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
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};
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static const unsigned int drif0_ctrl_a_mux[] = {
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RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
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};
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static const unsigned int drif0_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 10),
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};
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static const unsigned int drif0_data0_a_mux[] = {
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RIF0_D0_A_MARK,
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};
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static const unsigned int drif0_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 7),
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};
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static const unsigned int drif0_data1_a_mux[] = {
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RIF0_D1_A_MARK,
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};
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static const unsigned int drif0_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int drif0_ctrl_b_mux[] = {
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RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
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};
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static const unsigned int drif0_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 1),
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};
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static const unsigned int drif0_data0_b_mux[] = {
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RIF0_D0_B_MARK,
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};
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static const unsigned int drif0_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 2),
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};
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static const unsigned int drif0_data1_b_mux[] = {
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RIF0_D1_B_MARK,
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};
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static const unsigned int drif0_ctrl_c_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
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};
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static const unsigned int drif0_ctrl_c_mux[] = {
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RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
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};
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static const unsigned int drif0_data0_c_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 13),
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};
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static const unsigned int drif0_data0_c_mux[] = {
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RIF0_D0_C_MARK,
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};
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static const unsigned int drif0_data1_c_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 14),
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};
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||||
static const unsigned int drif0_data1_c_mux[] = {
|
||||
RIF0_D1_C_MARK,
|
||||
};
|
||||
/* - DRIF1 --------------------------------------------------------------- */
|
||||
static const unsigned int drif1_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int drif1_ctrl_a_mux[] = {
|
||||
RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
static const unsigned int drif1_data0_a_mux[] = {
|
||||
RIF1_D0_A_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 20),
|
||||
};
|
||||
static const unsigned int drif1_data1_a_mux[] = {
|
||||
RIF1_D1_A_MARK,
|
||||
};
|
||||
static const unsigned int drif1_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
|
||||
};
|
||||
static const unsigned int drif1_ctrl_b_mux[] = {
|
||||
RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 7),
|
||||
};
|
||||
static const unsigned int drif1_data0_b_mux[] = {
|
||||
RIF1_D0_B_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
static const unsigned int drif1_data1_b_mux[] = {
|
||||
RIF1_D1_B_MARK,
|
||||
};
|
||||
static const unsigned int drif1_ctrl_c_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
static const unsigned int drif1_ctrl_c_mux[] = {
|
||||
RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data0_c_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
static const unsigned int drif1_data0_c_mux[] = {
|
||||
RIF1_D0_C_MARK,
|
||||
};
|
||||
static const unsigned int drif1_data1_c_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int drif1_data1_c_mux[] = {
|
||||
RIF1_D1_C_MARK,
|
||||
};
|
||||
/* - DRIF2 --------------------------------------------------------------- */
|
||||
static const unsigned int drif2_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
};
|
||||
static const unsigned int drif2_ctrl_a_mux[] = {
|
||||
RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
|
||||
};
|
||||
static const unsigned int drif2_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 7),
|
||||
};
|
||||
static const unsigned int drif2_data0_a_mux[] = {
|
||||
RIF2_D0_A_MARK,
|
||||
};
|
||||
static const unsigned int drif2_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int drif2_data1_a_mux[] = {
|
||||
RIF2_D1_A_MARK,
|
||||
};
|
||||
static const unsigned int drif2_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
|
||||
};
|
||||
static const unsigned int drif2_ctrl_b_mux[] = {
|
||||
RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
|
||||
};
|
||||
static const unsigned int drif2_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 30),
|
||||
};
|
||||
static const unsigned int drif2_data0_b_mux[] = {
|
||||
RIF2_D0_B_MARK,
|
||||
};
|
||||
static const unsigned int drif2_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int drif2_data1_b_mux[] = {
|
||||
RIF2_D1_B_MARK,
|
||||
};
|
||||
/* - DRIF3 --------------------------------------------------------------- */
|
||||
static const unsigned int drif3_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int drif3_ctrl_a_mux[] = {
|
||||
RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
|
||||
};
|
||||
static const unsigned int drif3_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
static const unsigned int drif3_data0_a_mux[] = {
|
||||
RIF3_D0_A_MARK,
|
||||
};
|
||||
static const unsigned int drif3_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 20),
|
||||
};
|
||||
static const unsigned int drif3_data1_a_mux[] = {
|
||||
RIF3_D1_A_MARK,
|
||||
};
|
||||
static const unsigned int drif3_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
};
|
||||
static const unsigned int drif3_ctrl_b_mux[] = {
|
||||
RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
|
||||
};
|
||||
static const unsigned int drif3_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
static const unsigned int drif3_data0_b_mux[] = {
|
||||
RIF3_D0_B_MARK,
|
||||
};
|
||||
static const unsigned int drif3_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int drif3_data1_b_mux[] = {
|
||||
RIF3_D1_B_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int hscif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3346,6 +3563,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(canfd0_data_a),
|
||||
SH_PFC_PIN_GROUP(canfd0_data_b),
|
||||
SH_PFC_PIN_GROUP(canfd1_data),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_c),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_c),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_c),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_c),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_c),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_c),
|
||||
SH_PFC_PIN_GROUP(drif2_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif2_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif2_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif2_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif2_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif2_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif3_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
|
|
@ -3629,6 +3876,48 @@ static const char * const canfd1_groups[] = {
|
|||
"canfd1_data",
|
||||
};
|
||||
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
"drif0_data1_a",
|
||||
"drif0_ctrl_b",
|
||||
"drif0_data0_b",
|
||||
"drif0_data1_b",
|
||||
"drif0_ctrl_c",
|
||||
"drif0_data0_c",
|
||||
"drif0_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif1_groups[] = {
|
||||
"drif1_ctrl_a",
|
||||
"drif1_data0_a",
|
||||
"drif1_data1_a",
|
||||
"drif1_ctrl_b",
|
||||
"drif1_data0_b",
|
||||
"drif1_data1_b",
|
||||
"drif1_ctrl_c",
|
||||
"drif1_data0_c",
|
||||
"drif1_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif2_groups[] = {
|
||||
"drif2_ctrl_a",
|
||||
"drif2_data0_a",
|
||||
"drif2_data1_a",
|
||||
"drif2_ctrl_b",
|
||||
"drif2_data0_b",
|
||||
"drif2_data1_b",
|
||||
};
|
||||
|
||||
static const char * const drif3_groups[] = {
|
||||
"drif3_ctrl_a",
|
||||
"drif3_data0_a",
|
||||
"drif3_data1_a",
|
||||
"drif3_ctrl_b",
|
||||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
"hscif0_data",
|
||||
"hscif0_clk",
|
||||
|
|
@ -3972,6 +4261,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(canfd0),
|
||||
SH_PFC_FUNCTION(canfd1),
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
|
|
@ -4765,8 +5058,28 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ },
|
||||
};
|
||||
|
||||
static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
|
||||
bit = pin & 0x1f;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
|
||||
bit = (pin & 0x1f) + 12;
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
.name = "r8a77950_pfc",
|
||||
.ops = &r8a7795_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
|
|
@ -1625,7 +1625,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
GPIO_FN(VBIOS_CS),
|
||||
|
||||
/* PTW (mobule: LBSC, EVC, SCIF) */
|
||||
GPIO_FN(A16),
|
||||
GPIO_FN(A15),
|
||||
GPIO_FN(A14),
|
||||
GPIO_FN(A13),
|
||||
|
|
|
|||
|
|
@ -632,19 +632,21 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
}
|
||||
|
||||
case PIN_CONFIG_POWER_SOURCE: {
|
||||
int ret;
|
||||
u32 pocctrl, val;
|
||||
int bit;
|
||||
|
||||
if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)
|
||||
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
|
||||
return -ENOTSUPP;
|
||||
|
||||
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
|
||||
if (WARN(bit < 0, "invalid pin %#x", _pin))
|
||||
return bit;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
ret = pfc->info->ops->get_io_voltage(pfc, _pin);
|
||||
val = sh_pfc_read_reg(pfc, pocctrl, 32);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
*config = ret;
|
||||
*config = (val & BIT(bit)) ? 3300 : 1800;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -696,19 +698,28 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
}
|
||||
|
||||
case PIN_CONFIG_POWER_SOURCE: {
|
||||
unsigned int arg =
|
||||
pinconf_to_config_argument(configs[i]);
|
||||
int ret;
|
||||
unsigned int mV = pinconf_to_config_argument(configs[i]);
|
||||
u32 pocctrl, val;
|
||||
int bit;
|
||||
|
||||
if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)
|
||||
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
|
||||
return -ENOTSUPP;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
|
||||
if (WARN(bit < 0, "invalid pin %#x", _pin))
|
||||
return bit;
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
if (mV != 1800 && mV != 3300)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
val = sh_pfc_read_reg(pfc, pocctrl, 32);
|
||||
if (mV == 3300)
|
||||
val |= BIT(bit);
|
||||
else
|
||||
val &= ~BIT(bit);
|
||||
sh_pfc_write_reg(pfc, pocctrl, 32, val);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
enum {
|
||||
|
|
@ -182,16 +183,38 @@ struct pinmux_range {
|
|||
u16 force;
|
||||
};
|
||||
|
||||
struct sh_pfc;
|
||||
struct sh_pfc_window {
|
||||
phys_addr_t phys;
|
||||
void __iomem *virt;
|
||||
unsigned long size;
|
||||
};
|
||||
|
||||
struct sh_pfc_pin_range;
|
||||
|
||||
struct sh_pfc {
|
||||
struct device *dev;
|
||||
const struct sh_pfc_soc_info *info;
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned int num_windows;
|
||||
struct sh_pfc_window *windows;
|
||||
unsigned int num_irqs;
|
||||
unsigned int *irqs;
|
||||
|
||||
struct sh_pfc_pin_range *ranges;
|
||||
unsigned int nr_ranges;
|
||||
|
||||
unsigned int nr_gpio_pins;
|
||||
|
||||
struct sh_pfc_chip *gpio;
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_operations {
|
||||
int (*init)(struct sh_pfc *pfc);
|
||||
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
|
||||
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
|
||||
int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
|
||||
u16 voltage_mV);
|
||||
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info {
|
||||
|
|
@ -227,6 +250,30 @@ struct sh_pfc_soc_info {
|
|||
u32 unlock_reg;
|
||||
};
|
||||
|
||||
extern const struct sh_pfc_soc_info emev2_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info sh7203_pinmux_info;
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extern const struct sh_pfc_soc_info sh7264_pinmux_info;
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extern const struct sh_pfc_soc_info sh7269_pinmux_info;
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extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
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extern const struct sh_pfc_soc_info sh7720_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7722_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7723_pinmux_info;
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extern const struct sh_pfc_soc_info sh7724_pinmux_info;
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||||
extern const struct sh_pfc_soc_info sh7734_pinmux_info;
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||||
extern const struct sh_pfc_soc_info sh7757_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7785_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7786_pinmux_info;
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extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
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|
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/* -----------------------------------------------------------------------------
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* Helper macros to create pin and port lists
|
||||
*/
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