clk: imx: scu: add gpr clocks support
SCU clock protocol supports a few clocks based on GPR controller registers including mux/divider/gate. Add a generic clock register API to support them all. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
This commit is contained in:
Dong Aisheng
Abel Vesa
Родитель
91e916771d
Коммит
5392c5de09
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@ -52,6 +52,22 @@ struct clk_scu {
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u32 rate;
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};
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/*
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* struct clk_gpr_scu - Description of one SCU GPR clock
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* @hw: the common clk_hw
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* @rsrc_id: resource ID of this SCU clock
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* @gpr_id: GPR ID index to control the divider
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*/
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struct clk_gpr_scu {
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struct clk_hw hw;
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u16 rsrc_id;
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u8 gpr_id;
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u8 flags;
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bool gate_invert;
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};
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#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
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/*
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* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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* @hdr: SCU protocol header
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@ -605,3 +621,173 @@ void imx_clk_scu_unregister(void)
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}
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}
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}
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static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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unsigned long rate = 0;
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u32 val;
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int err;
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err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, &val);
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rate = val ? parent_rate / 2 : parent_rate;
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return err ? 0 : rate;
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}
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static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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if (rate < *prate)
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rate = *prate / 2;
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else
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rate = *prate;
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return rate;
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}
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static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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uint32_t val;
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int err;
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val = (rate < parent_rate) ? 1 : 0;
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err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, val);
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return err ? -EINVAL : 0;
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}
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static const struct clk_ops clk_gpr_div_scu_ops = {
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.recalc_rate = clk_gpr_div_scu_recalc_rate,
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.round_rate = clk_gpr_div_scu_round_rate,
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.set_rate = clk_gpr_div_scu_set_rate,
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};
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static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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u32 val = 0;
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imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, &val);
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return (u8)val;
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}
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static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, index);
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}
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static const struct clk_ops clk_gpr_mux_scu_ops = {
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.get_parent = clk_gpr_mux_scu_get_parent,
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.set_parent = clk_gpr_mux_scu_set_parent,
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};
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static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, !clk->gate_invert);
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}
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static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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int ret;
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ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, clk->gate_invert);
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if (ret)
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pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
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ret);
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}
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static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
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{
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struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
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int ret;
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u32 val;
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ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, &val);
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if (ret)
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return ret;
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return clk->gate_invert ? !val : val;
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}
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static const struct clk_ops clk_gpr_gate_scu_ops = {
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.prepare = clk_gpr_gate_scu_prepare,
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.unprepare = clk_gpr_gate_scu_unprepare,
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.is_prepared = clk_gpr_gate_scu_is_prepared,
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};
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struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
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int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
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bool invert)
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{
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struct imx_scu_clk_node *clk_node;
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struct clk_gpr_scu *clk;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
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return ERR_PTR(-EINVAL);
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clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
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if (!clk_node)
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return ERR_PTR(-ENOMEM);
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clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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if (!clk) {
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kfree(clk_node);
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return ERR_PTR(-ENOMEM);
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}
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clk->rsrc_id = rsrc_id;
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clk->gpr_id = gpr_id;
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clk->flags = flags;
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clk->gate_invert = invert;
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if (flags & IMX_SCU_GPR_CLK_GATE)
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init.ops = &clk_gpr_gate_scu_ops;
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if (flags & IMX_SCU_GPR_CLK_DIV)
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init.ops = &clk_gpr_div_scu_ops;
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if (flags & IMX_SCU_GPR_CLK_MUX)
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init.ops = &clk_gpr_mux_scu_ops;
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init.flags = 0;
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init.name = name;
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init.parent_names = parent_name;
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init.num_parents = num_parents;
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clk->hw.init = &init;
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hw = &clk->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(clk);
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kfree(clk_node);
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hw = ERR_PTR(ret);
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} else {
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clk_node->hw = hw;
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clk_node->clk_type = gpr_id;
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list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
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}
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return hw;
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}
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@ -10,6 +10,10 @@
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#include <linux/firmware/imx/sci.h>
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#include <linux/of.h>
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#define IMX_SCU_GPR_CLK_GATE BIT(0)
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#define IMX_SCU_GPR_CLK_DIV BIT(1)
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#define IMX_SCU_GPR_CLK_MUX BIT(2)
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extern struct list_head imx_scu_clks[];
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extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
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@ -31,6 +35,10 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
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void __iomem *reg, u8 bit_idx, bool hw_gate);
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void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
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struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
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int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
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bool invert);
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static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
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u8 clk_type)
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{
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@ -58,4 +66,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
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return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
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bit_idx, hw_gate);
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}
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static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
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u32 rsrc_id, u8 gpr_id, bool invert)
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{
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return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
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IMX_SCU_GPR_CLK_GATE, invert);
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}
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static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
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u32 rsrc_id, u8 gpr_id)
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{
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return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
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IMX_SCU_GPR_CLK_DIV, 0);
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}
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static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
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int num_parents, u32 rsrc_id, u8 gpr_id)
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{
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return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
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gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
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}
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#endif
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