Merge branch 'topic/ppc-kvm' into next
Merge the topic branch we share with kvm-ppc, this brings in two xive commits, one from Paul to rework HMI handling, and a minor cleanup to drop an unused flag.
This commit is contained in:
Michael Ellerman
Коммит
5400fc229e
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@ -42,4 +42,8 @@ extern void wait_for_tb_resync(void);
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static inline void wait_for_subcore_guest_exit(void) { }
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static inline void wait_for_tb_resync(void) { }
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#endif
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struct pt_regs;
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extern long hmi_handle_debugtrig(struct pt_regs *regs);
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#endif /* __ASM_PPC64_HMI_H__ */
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@ -241,6 +241,7 @@
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#define H_GET_HCA_INFO 0x1B8
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#define H_GET_PERF_COUNT 0x1BC
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#define H_MANAGE_TRACE 0x1C0
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#define H_GET_CPU_CHARACTERISTICS 0x1C8
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#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
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#define H_QUERY_INT_STATE 0x1E4
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#define H_POLL_PENDING 0x1D8
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@ -330,6 +331,17 @@
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#define H_SIGNAL_SYS_RESET_ALL_OTHERS -2
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/* >= 0 values are CPU number */
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/* H_GET_CPU_CHARACTERISTICS return values */
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#define H_CPU_CHAR_SPEC_BAR_ORI31 (1ull << 63) // IBM bit 0
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#define H_CPU_CHAR_BCCTRL_SERIALISED (1ull << 62) // IBM bit 1
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#define H_CPU_CHAR_L1D_FLUSH_ORI30 (1ull << 61) // IBM bit 2
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#define H_CPU_CHAR_L1D_FLUSH_TRIG2 (1ull << 60) // IBM bit 3
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#define H_CPU_CHAR_L1D_THREAD_PRIV (1ull << 59) // IBM bit 4
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#define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
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#define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
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#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ull << 61) // IBM bit 2
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/* Flag values used in H_REGISTER_PROC_TBL hcall */
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#define PROC_TABLE_OP_MASK 0x18
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#define PROC_TABLE_DEREG 0x10
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@ -436,6 +448,11 @@ static inline unsigned int get_longbusy_msecs(int longbusy_rc)
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}
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}
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struct h_cpu_char_result {
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u64 character;
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u64 behaviour;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_HVCALL_H */
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@ -326,4 +326,18 @@ static inline long plapr_signal_sys_reset(long cpu)
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return plpar_hcall_norets(H_SIGNAL_SYS_RESET, cpu);
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}
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static inline long plpar_get_cpu_characteristics(struct h_cpu_char_result *p)
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{
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unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
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long rc;
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rc = plpar_hcall(H_GET_CPU_CHARACTERISTICS, retbuf);
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if (rc == H_SUCCESS) {
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p->character = retbuf[0];
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p->behaviour = retbuf[1];
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}
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return rc;
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}
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#endif /* _ASM_POWERPC_PLPAR_WRAPPERS_H */
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@ -431,8 +431,9 @@
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#define SPRN_LPID 0x13F /* Logical Partition Identifier */
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#endif
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#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */
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#define SPRN_HMER 0x150 /* Hardware m? error recovery */
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#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
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#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */
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#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */
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#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */
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#define SPRN_PCR 0x152 /* Processor compatibility register */
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#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
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#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
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@ -9,6 +9,41 @@
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#ifndef _ASM_POWERPC_XIVE_REGS_H
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#define _ASM_POWERPC_XIVE_REGS_H
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/*
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* "magic" Event State Buffer (ESB) MMIO offsets.
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*
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* Each interrupt source has a 2-bit state machine called ESB
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* which can be controlled by MMIO. It's made of 2 bits, P and
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* Q. P indicates that an interrupt is pending (has been sent
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* to a queue and is waiting for an EOI). Q indicates that the
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* interrupt has been triggered while pending.
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*
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* This acts as a coalescing mechanism in order to guarantee
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* that a given interrupt only occurs at most once in a queue.
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*
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* When doing an EOI, the Q bit will indicate if the interrupt
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* needs to be re-triggered.
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*
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* The following offsets into the ESB MMIO allow to read or
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* manipulate the PQ bits. They must be used with an 8-bytes
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* load instruction. They all return the previous state of the
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* interrupt (atomically).
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*
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* Additionally, some ESB pages support doing an EOI via a
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* store at 0 and some ESBs support doing a trigger via a
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* separate trigger page.
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*/
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
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#define XIVE_ESB_GET 0x800 /* Load */
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
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#define XIVE_ESB_VAL_P 0x2
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#define XIVE_ESB_VAL_Q 0x1
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/*
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* Thread Management (aka "TM") registers
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*/
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@ -58,6 +58,9 @@ struct xive_irq_data {
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#define XIVE_IRQ_FLAG_EOI_FW 0x10
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#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
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/* Special flag set by KVM for excalation interrupts */
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#define XIVE_IRQ_NO_EOI 0x80
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#define XIVE_INVALID_CHIP_ID -1
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/* A queue tracking structure in a CPU */
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@ -72,41 +75,6 @@ struct xive_q {
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atomic_t pending_count;
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};
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/*
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* "magic" Event State Buffer (ESB) MMIO offsets.
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*
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* Each interrupt source has a 2-bit state machine called ESB
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* which can be controlled by MMIO. It's made of 2 bits, P and
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* Q. P indicates that an interrupt is pending (has been sent
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* to a queue and is waiting for an EOI). Q indicates that the
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* interrupt has been triggered while pending.
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*
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* This acts as a coalescing mechanism in order to guarantee
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* that a given interrupt only occurs at most once in a queue.
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*
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* When doing an EOI, the Q bit will indicate if the interrupt
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* needs to be re-triggered.
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*
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* The following offsets into the ESB MMIO allow to read or
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* manipulate the PQ bits. They must be used with an 8-bytes
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* load instruction. They all return the previous state of the
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* interrupt (atomically).
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*
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* Additionally, some ESB pages support doing an EOI via a
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* store at 0 and some ESBs support doing a trigger via a
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* separate trigger page.
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*/
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
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#define XIVE_ESB_GET 0x800 /* Load */
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
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#define XIVE_ESB_VAL_P 0x2
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#define XIVE_ESB_VAL_Q 0x1
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/* Global enable flags for the XIVE support */
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extern bool __xive_enabled;
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@ -495,37 +495,123 @@ long machine_check_early(struct pt_regs *regs)
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return handled;
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}
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long hmi_exception_realmode(struct pt_regs *regs)
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/* Possible meanings for HMER_DEBUG_TRIG bit being set on POWER9 */
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static enum {
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DTRIG_UNKNOWN,
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DTRIG_VECTOR_CI, /* need to emulate vector CI load instr */
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DTRIG_SUSPEND_ESCAPE, /* need to escape from TM suspend mode */
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} hmer_debug_trig_function;
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static int init_debug_trig_function(void)
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{
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int pvr;
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struct device_node *cpun;
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struct property *prop = NULL;
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const char *str;
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/* First look in the device tree */
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preempt_disable();
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cpun = of_get_cpu_node(smp_processor_id(), NULL);
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if (cpun) {
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of_property_for_each_string(cpun, "ibm,hmi-special-triggers",
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prop, str) {
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if (strcmp(str, "bit17-vector-ci-load") == 0)
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hmer_debug_trig_function = DTRIG_VECTOR_CI;
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else if (strcmp(str, "bit17-tm-suspend-escape") == 0)
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hmer_debug_trig_function = DTRIG_SUSPEND_ESCAPE;
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}
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of_node_put(cpun);
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}
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preempt_enable();
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/* If we found the property, don't look at PVR */
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if (prop)
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goto out;
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pvr = mfspr(SPRN_PVR);
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/* Check for POWER9 Nimbus (scale-out) */
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if ((PVR_VER(pvr) == PVR_POWER9) && (pvr & 0xe000) == 0) {
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/* DD2.2 and later */
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if ((pvr & 0xfff) >= 0x202)
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hmer_debug_trig_function = DTRIG_SUSPEND_ESCAPE;
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/* DD2.0 and DD2.1 - used for vector CI load emulation */
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else if ((pvr & 0xfff) >= 0x200)
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hmer_debug_trig_function = DTRIG_VECTOR_CI;
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}
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out:
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switch (hmer_debug_trig_function) {
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case DTRIG_VECTOR_CI:
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pr_debug("HMI debug trigger used for vector CI load\n");
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break;
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case DTRIG_SUSPEND_ESCAPE:
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pr_debug("HMI debug trigger used for TM suspend escape\n");
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break;
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default:
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break;
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}
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return 0;
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}
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__initcall(init_debug_trig_function);
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/*
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* Handle HMIs that occur as a result of a debug trigger.
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* Return values:
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* -1 means this is not a HMI cause that we know about
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* 0 means no further handling is required
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* 1 means further handling is required
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*/
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long hmi_handle_debugtrig(struct pt_regs *regs)
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{
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unsigned long hmer = mfspr(SPRN_HMER);
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long ret = 0;
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/* HMER_DEBUG_TRIG bit is used for various workarounds on P9 */
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if (!((hmer & HMER_DEBUG_TRIG)
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&& hmer_debug_trig_function != DTRIG_UNKNOWN))
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return -1;
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hmer &= ~HMER_DEBUG_TRIG;
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/* HMER is a write-AND register */
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mtspr(SPRN_HMER, ~HMER_DEBUG_TRIG);
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switch (hmer_debug_trig_function) {
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case DTRIG_VECTOR_CI:
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/*
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* Now to avoid problems with soft-disable we
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* only do the emulation if we are coming from
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* host user space
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*/
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if (regs && user_mode(regs))
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ret = local_paca->hmi_p9_special_emu = 1;
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break;
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default:
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break;
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}
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|
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/*
|
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* See if any other HMI causes remain to be handled
|
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*/
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if (hmer & mfspr(SPRN_HMEER))
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return -1;
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return ret;
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}
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|
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/*
|
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* Return values:
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*/
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long hmi_exception_realmode(struct pt_regs *regs)
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{
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int ret;
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|
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__this_cpu_inc(irq_stat.hmi_exceptions);
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|
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#ifdef CONFIG_PPC_BOOK3S_64
|
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/* Workaround for P9 vector CI loads (see p9_hmi_special_emu) */
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if (pvr_version_is(PVR_POWER9)) {
|
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unsigned long hmer = mfspr(SPRN_HMER);
|
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|
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/* Do we have the debug bit set */
|
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if (hmer & PPC_BIT(17)) {
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hmer &= ~PPC_BIT(17);
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mtspr(SPRN_HMER, hmer);
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|
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/*
|
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* Now to avoid problems with soft-disable we
|
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* only do the emulation if we are coming from
|
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* user space
|
||||
*/
|
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if (user_mode(regs))
|
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local_paca->hmi_p9_special_emu = 1;
|
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|
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/*
|
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* Don't bother going to OPAL if that's the
|
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* only relevant bit.
|
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*/
|
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if (!(hmer & mfspr(SPRN_HMEER)))
|
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return local_paca->hmi_p9_special_emu;
|
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}
|
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}
|
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#endif /* CONFIG_PPC_BOOK3S_64 */
|
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ret = hmi_handle_debugtrig(regs);
|
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if (ret >= 0)
|
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return ret;
|
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|
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wait_for_subcore_guest_exit();
|
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|
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|
|
|
|||
|
|
@ -266,17 +266,19 @@ static void kvmppc_tb_resync_done(void)
|
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* secondary threads to proceed.
|
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* - All secondary threads will eventually call opal hmi handler on
|
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* their exit path.
|
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*
|
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* Returns 1 if the timebase offset should be applied, 0 if not.
|
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*/
|
||||
|
||||
long kvmppc_realmode_hmi_handler(void)
|
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{
|
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int ptid = local_paca->kvm_hstate.ptid;
|
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bool resync_req;
|
||||
|
||||
/* This is only called on primary thread. */
|
||||
BUG_ON(ptid != 0);
|
||||
__this_cpu_inc(irq_stat.hmi_exceptions);
|
||||
|
||||
if (hmi_handle_debugtrig(NULL) >= 0)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* By now primary thread has already completed guest->host
|
||||
* partition switch but haven't signaled secondaries yet.
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static void *real_vmalloc_addr(void *x)
|
|||
}
|
||||
|
||||
/* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
|
||||
static int global_invalidates(struct kvm *kvm, unsigned long flags)
|
||||
static int global_invalidates(struct kvm *kvm)
|
||||
{
|
||||
int global;
|
||||
int cpu;
|
||||
|
|
@ -522,7 +522,7 @@ long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
|
|||
if (v & HPTE_V_VALID) {
|
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hpte[0] &= ~cpu_to_be64(HPTE_V_VALID);
|
||||
rb = compute_tlbie_rb(v, pte_r, pte_index);
|
||||
do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags), true);
|
||||
do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
|
||||
/*
|
||||
* The reference (R) and change (C) bits in a HPT
|
||||
* entry can be set by hardware at any time up until
|
||||
|
|
@ -572,7 +572,7 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
|
|||
|
||||
if (kvm_is_radix(kvm))
|
||||
return H_FUNCTION;
|
||||
global = global_invalidates(kvm, 0);
|
||||
global = global_invalidates(kvm);
|
||||
for (i = 0; i < 4 && ret == H_SUCCESS; ) {
|
||||
n = 0;
|
||||
for (; i < 4; ++i) {
|
||||
|
|
@ -732,8 +732,7 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
|
|||
rb = compute_tlbie_rb(v, r, pte_index);
|
||||
hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) |
|
||||
HPTE_V_ABSENT);
|
||||
do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags),
|
||||
true);
|
||||
do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
|
||||
/* Don't lose R/C bit updates done by hardware */
|
||||
r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C);
|
||||
hpte[1] = cpu_to_be64(r);
|
||||
|
|
|
|||
|
|
@ -1909,16 +1909,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
|||
bne 27f
|
||||
bl kvmppc_realmode_hmi_handler
|
||||
nop
|
||||
cmpdi r3, 0
|
||||
li r12, BOOK3S_INTERRUPT_HMI
|
||||
/*
|
||||
* At this point kvmppc_realmode_hmi_handler would have resync-ed
|
||||
* the TB. Hence it is not required to subtract guest timebase
|
||||
* offset from timebase. So, skip it.
|
||||
* At this point kvmppc_realmode_hmi_handler may have resync-ed
|
||||
* the TB, and if it has, we must not subtract the guest timebase
|
||||
* offset from the timebase. So, skip it.
|
||||
*
|
||||
* Also, do not call kvmppc_subcore_exit_guest() because it has
|
||||
* been invoked as part of kvmppc_realmode_hmi_handler().
|
||||
*/
|
||||
b 30f
|
||||
beq 30f
|
||||
|
||||
27:
|
||||
/* Subtract timebase offset from timebase */
|
||||
|
|
|
|||
|
|
@ -367,7 +367,8 @@ static void xive_irq_eoi(struct irq_data *d)
|
|||
* EOI the source if it hasn't been disabled and hasn't
|
||||
* been passed-through to a KVM guest
|
||||
*/
|
||||
if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d))
|
||||
if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
|
||||
!(xd->flags & XIVE_IRQ_NO_EOI))
|
||||
xive_do_source_eoi(irqd_to_hwirq(d), xd);
|
||||
|
||||
/*
|
||||
|
|
|
|||
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