firmware: qcom_scm: Apply consistent naming scheme to command IDs
Create a consistent naming scheme for command IDs. The scheme is QCOM_SCM_##svc_##cmd. Remove unused macros QCOM_SCM_FLAG_HLOS, QCOM_SCM_FLAG_COLDBOOT_MC, QCOM_SCM_FLAG_WARMBOOT_MC, QCOM_SCM_CMD_CORE_HOTPLUGGED, and QCOM_SCM_BOOT_ADDR_MC. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-3-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Elliot Berman
Bjorn Andersson
Родитель
e0aa153965
Коммит
5443cc5f12
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@ -357,7 +357,7 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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set_cpu_present(cpu, false);
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}
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
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flags, virt_to_phys(entry));
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}
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@ -396,7 +396,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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cmd.addr = cpu_to_le32(virt_to_phys(entry));
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cmd.flags = cpu_to_le32(flags);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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if (!ret) {
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for_each_cpu(cpu, cpus)
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@ -416,7 +416,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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*/
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void __qcom_scm_cpu_power_down(u32 flags)
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{
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qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
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qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC,
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flags & QCOM_SCM_FLUSH_FLAG_MASK);
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}
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@ -426,7 +426,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
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__le32 ret_val = 0;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&svc_cmd, sizeof(svc_cmd), &ret_val,
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sizeof(ret_val));
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if (ret)
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@ -441,7 +441,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP,
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE,
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req, req_cnt * sizeof(*req), resp, sizeof(*resp));
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}
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@ -460,7 +460,7 @@ int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,
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request.size = cpu_to_le32(size);
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request.mode = cpu_to_le32(mode);
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return qcom_scm_call(dev, QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
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return qcom_scm_call(dev, QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_LOCK_CMD,
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&request, sizeof(request), NULL, 0);
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}
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@ -476,7 +476,7 @@ int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)
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request.offset = cpu_to_le32(offset);
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request.size = cpu_to_le32(size);
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return qcom_scm_call(dev, QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
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return qcom_scm_call(dev, QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_UNLOCK_CMD,
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&request, sizeof(request), NULL, 0);
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}
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@ -492,7 +492,7 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD,
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QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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&in, sizeof(in),
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&out, sizeof(out));
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@ -513,7 +513,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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request.image_addr = cpu_to_le32(metadata_phys);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_INIT_IMAGE_CMD,
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QCOM_SCM_PIL_PAS_INIT_IMAGE,
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&request, sizeof(request),
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&scm_ret, sizeof(scm_ret));
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@ -536,7 +536,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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request.len = cpu_to_le32(size);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_MEM_SETUP_CMD,
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QCOM_SCM_PIL_PAS_MEM_SETUP,
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&request, sizeof(request),
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&scm_ret, sizeof(scm_ret));
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@ -551,7 +551,7 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_AUTH_AND_RESET_CMD,
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QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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&in, sizeof(in),
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&out, sizeof(out));
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@ -566,7 +566,7 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_SHUTDOWN_CMD,
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QCOM_SCM_PIL_PAS_SHUTDOWN,
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&in, sizeof(in),
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&out, sizeof(out));
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@ -579,7 +579,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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__le32 in = cpu_to_le32(reset);
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int ret;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET,
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&in, sizeof(in),
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&out, sizeof(out));
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@ -588,8 +588,8 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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{
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE,
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enable ? QCOM_SCM_SET_DLOAD_MODE : 0, 0);
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0);
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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@ -604,7 +604,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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req.state = cpu_to_le32(state);
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req.id = cpu_to_le32(id);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&req, sizeof(req), &scm_ret, sizeof(scm_ret));
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return ret ? : le32_to_cpu(scm_ret);
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@ -629,7 +629,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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cfg.id = cpu_to_le32(device_id);
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cfg.ctx_bank_num = cpu_to_le32(spare);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG,
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&cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
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if (ret || scm_ret)
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@ -257,7 +257,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&desc, &res);
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return ret ? : res.a1;
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@ -285,7 +285,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(10);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, &desc,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc,
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&res);
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*resp = res.a1;
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@ -308,11 +308,11 @@ void __qcom_scm_init(void)
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{
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u64 cmd;
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struct arm_smccc_res res;
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u32 function = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD);
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u32 fnid = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL);
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/* First try a SMC64 call */
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cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
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ARM_SMCCC_OWNER_SIP, function);
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ARM_SMCCC_OWNER_SIP, fnid);
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arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
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0, 0, 0, 0, 0, &res);
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@ -333,7 +333,7 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD,
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QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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&desc, &res);
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return ret ? false : !!res.a1;
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@ -350,7 +350,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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desc.args[1] = metadata_phys;
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desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_INIT_IMAGE_CMD,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_INIT_IMAGE,
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&desc, &res);
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return ret ? : res.a1;
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@ -368,7 +368,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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desc.args[2] = size;
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desc.arginfo = QCOM_SCM_ARGS(3);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MEM_SETUP_CMD,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MEM_SETUP,
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&desc, &res);
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return ret ? : res.a1;
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@ -384,7 +384,7 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_AUTH_AND_RESET_CMD,
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QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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&desc, &res);
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return ret ? : res.a1;
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@ -399,7 +399,7 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_SHUTDOWN_CMD,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_SHUTDOWN,
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&desc, &res);
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return ret ? : res.a1;
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@ -415,7 +415,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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desc.args[1] = 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, &desc,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, &desc,
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&res);
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return ret ? : res.a1;
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@ -431,7 +431,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&desc, &res);
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return ret ? : res.a1;
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@ -458,7 +458,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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QCOM_SCM_VAL, QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_MEM_PROT_ASSIGN_ID,
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QCOM_SCM_MP_ASSIGN,
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&desc, &res);
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return ret ? : res.a1;
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@ -474,7 +474,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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desc.args[1] = spare;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG,
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&desc, &res);
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return ret ? : res.a1;
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@ -491,7 +491,7 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_SCM_IOMMU_SECURE_PTBL_SIZE, &desc, &res);
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QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, &desc, &res);
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if (size)
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*size = res.a1;
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@ -513,7 +513,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_SCM_IOMMU_SECURE_PTBL_INIT, &desc, &res);
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QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, &desc, &res);
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/* the pg table has been initialized already, ignore the error */
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if (ret == -EPERM)
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@ -527,11 +527,11 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_SET_DLOAD_MODE : 0;
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desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE,
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return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
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&desc, &res);
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}
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@ -571,10 +571,10 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL;
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desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
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desc.args[1] = en;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM,
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QCOM_SCM_CONFIG_ERRATA1, &desc, &res);
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QCOM_SCM_SMMU_CONFIG_ERRATA1, &desc, &res);
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}
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Qualcomm SCM driver
|
||||
*
|
||||
* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2015 Linaro Ltd.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -142,7 +139,7 @@ bool qcom_scm_hdcp_available(void)
|
|||
return ret;
|
||||
|
||||
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
|
||||
QCOM_SCM_CMD_HDCP);
|
||||
QCOM_SCM_HDCP_INVOKE);
|
||||
|
||||
qcom_scm_clk_disable();
|
||||
|
||||
|
|
@ -183,7 +180,7 @@ bool qcom_scm_pas_supported(u32 peripheral)
|
|||
int ret;
|
||||
|
||||
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
|
||||
QCOM_SCM_PAS_IS_SUPPORTED_CMD);
|
||||
QCOM_SCM_PIL_PAS_IS_SUPPORTED);
|
||||
if (ret <= 0)
|
||||
return false;
|
||||
|
||||
|
|
@ -196,7 +193,7 @@ EXPORT_SYMBOL(qcom_scm_pas_supported);
|
|||
*/
|
||||
bool qcom_scm_ocmem_lock_available(void)
|
||||
{
|
||||
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_OCMEM_SVC,
|
||||
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
|
||||
QCOM_SCM_OCMEM_LOCK_CMD);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
|
||||
|
|
@ -376,7 +373,7 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = {
|
|||
bool qcom_scm_restore_sec_cfg_available(void)
|
||||
{
|
||||
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
|
||||
QCOM_SCM_RESTORE_SEC_CFG);
|
||||
QCOM_SCM_MP_RESTORE_SEC_CFG);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
|
||||
|
||||
|
|
@ -423,12 +420,12 @@ static void qcom_scm_set_download_mode(bool enable)
|
|||
|
||||
avail = __qcom_scm_is_call_available(__scm->dev,
|
||||
QCOM_SCM_SVC_BOOT,
|
||||
QCOM_SCM_SET_DLOAD_MODE);
|
||||
QCOM_SCM_BOOT_SET_DLOAD_MODE);
|
||||
if (avail) {
|
||||
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
|
||||
} else if (__scm->dload_mode_addr) {
|
||||
ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
|
||||
enable ? QCOM_SCM_SET_DLOAD_MODE : 0);
|
||||
enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
|
||||
} else {
|
||||
dev_err(__scm->dev,
|
||||
"No available mechanism for setting download mode\n");
|
||||
|
|
|
|||
|
|
@ -1,27 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#ifndef __QCOM_SCM_INT_H
|
||||
#define __QCOM_SCM_INT_H
|
||||
|
||||
#define QCOM_SCM_SVC_BOOT 0x1
|
||||
#define QCOM_SCM_BOOT_ADDR 0x1
|
||||
#define QCOM_SCM_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_ADDR_MC 0x11
|
||||
#define QCOM_SCM_SET_REMOTE_STATE 0xa
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x1
|
||||
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa
|
||||
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
||||
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
||||
|
||||
#define QCOM_SCM_FLAG_HLOS 0x01
|
||||
#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
|
||||
#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
|
||||
extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
|
||||
const cpumask_t *cpus);
|
||||
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
|
||||
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x2
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
|
||||
extern void __qcom_scm_cpu_power_down(u32 flags);
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x5
|
||||
|
|
@ -31,18 +26,18 @@ extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned in
|
|||
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
||||
|
||||
#define QCOM_SCM_SVC_INFO 0x6
|
||||
#define QCOM_IS_CALL_AVAIL_CMD 0x1
|
||||
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1
|
||||
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
||||
u32 cmd_id);
|
||||
|
||||
#define QCOM_SCM_SVC_HDCP 0x11
|
||||
#define QCOM_SCM_CMD_HDCP 0x01
|
||||
#define QCOM_SCM_HDCP_INVOKE 0x01
|
||||
extern int __qcom_scm_hdcp_req(struct device *dev,
|
||||
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
||||
|
||||
extern void __qcom_scm_init(void);
|
||||
|
||||
#define QCOM_SCM_OCMEM_SVC 0xf
|
||||
#define QCOM_SCM_SVC_OCMEM 0xf
|
||||
#define QCOM_SCM_OCMEM_LOCK_CMD 0x1
|
||||
#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2
|
||||
|
||||
|
|
@ -52,12 +47,12 @@ extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
|
|||
u32 size);
|
||||
|
||||
#define QCOM_SCM_SVC_PIL 0x2
|
||||
#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
|
||||
#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
|
||||
#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
|
||||
#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
|
||||
#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
|
||||
#define QCOM_SCM_PAS_MSS_RESET 0xa
|
||||
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1
|
||||
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2
|
||||
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5
|
||||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa
|
||||
extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
|
||||
extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
|
||||
dma_addr_t metadata_phys);
|
||||
|
|
@ -95,21 +90,21 @@ static inline int qcom_scm_remap_error(int err)
|
|||
}
|
||||
|
||||
#define QCOM_SCM_SVC_MP 0xc
|
||||
#define QCOM_SCM_RESTORE_SEC_CFG 2
|
||||
#define QCOM_SCM_MP_RESTORE_SEC_CFG 2
|
||||
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
||||
u32 spare);
|
||||
#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3
|
||||
#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4
|
||||
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
||||
#define QCOM_SCM_CONFIG_ERRATA1 0x3
|
||||
#define QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
||||
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
||||
size_t *size);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
||||
u32 size, u32 spare);
|
||||
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
||||
bool enable);
|
||||
#define QCOM_MEM_PROT_ASSIGN_ID 0x16
|
||||
#define QCOM_SCM_MP_ASSIGN 0x16
|
||||
extern int __qcom_scm_assign_mem(struct device *dev,
|
||||
phys_addr_t mem_region, size_t mem_sz,
|
||||
phys_addr_t src, size_t src_sz,
|
||||
|
|
|
|||
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