clk: qcom: clk-alpha-pll: Add support for Trion PLLs
Add programming sequence support for managing the Trion PLLs. Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [vkoul: port to upstream and tidy-up use upstream way of specifying PLLs] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20190722074348.29582-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Deepak Katragadda
Stephen Boyd
Родитель
4c45653b0b
Коммит
548a909597
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@ -32,6 +32,7 @@
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# define PLL_LOCK_DET BIT(31)
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#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
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#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
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#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
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#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
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@ -44,14 +45,17 @@
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# define PLL_VCO_MASK 0x3
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#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
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#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
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#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
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#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
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#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
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#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
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#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
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#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
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#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
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#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
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#define PLL_CAL_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
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const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
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@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_OPMODE] = 0x2c,
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[PLL_OFF_FRAC] = 0x38,
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},
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[CLK_ALPHA_PLL_TYPE_TRION] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_CAL_L_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_USER_CTL_U1] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1c,
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[PLL_OFF_CONFIG_CTL_U1] = 0x20,
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[PLL_OFF_TEST_CTL] = 0x24,
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[PLL_OFF_TEST_CTL_U] = 0x28,
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[PLL_OFF_STATUS] = 0x30,
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[PLL_OFF_OPMODE] = 0x38,
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[PLL_OFF_ALPHA_VAL] = 0x40,
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[PLL_OFF_CAL_VAL] = 0x44,
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},
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define FABIA_PLL_OUT_MASK 0x7
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#define FABIA_PLL_RATE_MARGIN 500
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#define TRION_PLL_STANDBY 0x0
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#define TRION_PLL_RUN 0x1
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#define TRION_PLL_OUT_MASK 0x7
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
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@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
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return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
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}
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static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
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struct regmap *regmap)
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{
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u32 mode_regval, opmode_regval;
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int ret;
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ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
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ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
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if (ret)
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return 0;
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return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
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}
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static int clk_trion_pll_is_enabled(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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return trion_pll_is_enabled(pll, pll->clkr.regmap);
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}
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static int clk_trion_pll_enable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct regmap *regmap = pll->clkr.regmap;
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u32 val;
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int ret;
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ret = regmap_read(regmap, PLL_MODE(pll), &val);
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if (ret)
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return ret;
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/* If in FSM mode, just vote for it */
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if (val & PLL_VOTE_FSM_ENA) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll_enable_active(pll);
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}
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/* Set operation mode to RUN */
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regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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/* Enable the PLL outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
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if (ret)
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return ret;
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/* Enable the global PLL outputs */
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return regmap_update_bits(regmap, PLL_MODE(pll),
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PLL_OUTCTRL, PLL_OUTCTRL);
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}
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static void clk_trion_pll_disable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct regmap *regmap = pll->clkr.regmap;
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u32 val;
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int ret;
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ret = regmap_read(regmap, PLL_MODE(pll), &val);
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if (ret)
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return;
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/* If in FSM mode, just unvote it */
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if (val & PLL_VOTE_FSM_ENA) {
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clk_disable_regmap(hw);
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return;
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}
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/* Disable the global PLL output */
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return;
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/* Disable the PLL outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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TRION_PLL_OUT_MASK, 0);
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if (ret)
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return;
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/* Place the PLL mode in STANDBY */
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regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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static unsigned long
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clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct regmap *regmap = pll->clkr.regmap;
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u32 l, frac;
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u64 prate = parent_rate;
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regmap_read(regmap, PLL_L_VAL(pll), &l);
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regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
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return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
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}
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static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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unsigned long min_freq, max_freq;
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u32 l;
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u64 a;
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rate = alpha_pll_round_rate(rate, *prate,
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&l, &a, ALPHA_REG_16BIT_WIDTH);
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if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
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return rate;
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min_freq = pll->vco_table[0].min_freq;
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max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
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return clamp(rate, min_freq, max_freq);
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}
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const struct clk_ops clk_alpha_pll_ops = {
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.enable = clk_alpha_pll_enable,
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.disable = clk_alpha_pll_disable,
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@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
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const struct clk_ops clk_trion_fixed_pll_ops = {
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.enable = clk_trion_pll_enable,
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.disable = clk_trion_pll_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_trion_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
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static unsigned long
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clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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@ -1053,6 +1210,66 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
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return (parent_rate / div);
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}
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static unsigned long
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clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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struct regmap *regmap = pll->clkr.regmap;
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u32 i, div = 1, val;
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regmap_read(regmap, PLL_USER_CTL(pll), &val);
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val >>= pll->post_div_shift;
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val &= PLL_POST_DIV_MASK(pll);
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for (i = 0; i < pll->num_post_div; i++) {
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if (pll->post_div_table[i].val == val) {
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div = pll->post_div_table[i].div;
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break;
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}
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}
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return (parent_rate / div);
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}
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static long
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clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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return divider_round_rate(hw, rate, prate, pll->post_div_table,
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pll->width, CLK_DIVIDER_ROUND_CLOSEST);
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};
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static int
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clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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struct regmap *regmap = pll->clkr.regmap;
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int i, val = 0, div;
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div = DIV_ROUND_UP_ULL(parent_rate, rate);
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for (i = 0; i < pll->num_post_div; i++) {
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if (pll->post_div_table[i].div == div) {
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val = pll->post_div_table[i].val;
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break;
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}
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}
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return regmap_update_bits(regmap, PLL_USER_CTL(pll),
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PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
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val << PLL_POST_DIV_SHIFT);
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}
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const struct clk_ops clk_trion_pll_postdiv_ops = {
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.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
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.round_rate = clk_trion_pll_postdiv_round_rate,
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.set_rate = clk_trion_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
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static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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{
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@ -13,22 +13,27 @@ enum {
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CLK_ALPHA_PLL_TYPE_HUAYRA,
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CLK_ALPHA_PLL_TYPE_BRAMMO,
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CLK_ALPHA_PLL_TYPE_FABIA,
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CLK_ALPHA_PLL_TYPE_TRION,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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enum {
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PLL_OFF_L_VAL,
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PLL_OFF_CAL_L_VAL,
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PLL_OFF_ALPHA_VAL,
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PLL_OFF_ALPHA_VAL_U,
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PLL_OFF_USER_CTL,
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PLL_OFF_USER_CTL_U,
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PLL_OFF_USER_CTL_U1,
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PLL_OFF_CONFIG_CTL,
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PLL_OFF_CONFIG_CTL_U,
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PLL_OFF_CONFIG_CTL_U1,
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PLL_OFF_TEST_CTL,
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PLL_OFF_TEST_CTL_U,
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PLL_OFF_STATUS,
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PLL_OFF_OPMODE,
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PLL_OFF_FRAC,
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PLL_OFF_CAL_VAL,
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PLL_OFF_MAX_REGS
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};
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@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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extern const struct clk_ops clk_trion_fixed_pll_ops;
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extern const struct clk_ops clk_trion_pll_postdiv_ops;
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#endif
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