powerpc/40x: Remove EP405
EP405 is an old type of board based on a 405GP which is obsolete. Remove it. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/e9534caa51f327c841b3db5f48043a47ad70d246.1590079968.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
Родитель
5786074b96
Коммит
548f5244f1
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@ -130,7 +130,7 @@ src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
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src-wlib-$(CONFIG_CPM) += cpm-serial.c
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src-plat-y := of.c epapr.c
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src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
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src-plat-$(CONFIG_40x) += fixed-head.S cuboot-hotfoot.c \
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cuboot-acadia.c \
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cuboot-kilauea.c simpleboot.c
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src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
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@ -275,7 +275,6 @@ image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
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#
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# Board ports in arch/powerpc/platform/40x/Kconfig
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image-$(CONFIG_EP405) += dtbImage.ep405
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image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
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image-$(CONFIG_ACADIA) += cuImage.acadia
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image-$(CONFIG_OBS600) += uImage.obs600
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@ -1,230 +0,0 @@
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/*
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* Device Tree Source for EP405
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*
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* Copyright 2007 IBM Corp.
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "ep405";
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compatible = "ep405";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,405GP";
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reg = <0x00000000>;
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clock-frequency = <200000000>; /* Filled in by zImage */
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timebase-frequency = <0>; /* Filled in by zImage */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <16384>;
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d-cache-size = <16384>;
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000>; /* Filled in by zImage */
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};
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UIC0: interrupt-controller {
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compatible = "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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plb {
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compatible = "ibm,plb3";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by zImage */
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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MAL: mcmal {
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compatible = "ibm,mcmal-405gp", "ibm,mcmal";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <1>;
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num-rx-chans = <1>;
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interrupt-parent = <&UIC0>;
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interrupts = <
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0xb 0x4 /* TXEOB */
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0xc 0x4 /* RXEOB */
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0xa 0x4 /* SERR */
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0xd 0x4 /* TXDE */
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0xe 0x4 /* RXDE */>;
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};
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POB0: opb {
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compatible = "ibm,opb-405gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xef600000 0xef600000 0x00a00000>;
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dcr-reg = <0x0a0 0x005>;
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clock-frequency = <0>; /* Filled in by zImage */
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 0x00000008>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <9600>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x0 0x4>;
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};
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UART1: serial@ef600400 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600400 0x00000008>;
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virtual-reg = <0xef600400>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <9600>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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IIC: i2c@ef600500 {
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compatible = "ibm,iic-405gp", "ibm,iic";
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reg = <0xef600500 0x00000011>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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};
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GPIO: gpio@ef600700 {
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compatible = "ibm,gpio-405gp";
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reg = <0xef600700 0x00000020>;
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};
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EMAC: ethernet@ef600800 {
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linux,network-index = <0x0>;
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device_type = "network";
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compatible = "ibm,emac-405gp", "ibm,emac";
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interrupt-parent = <&UIC0>;
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interrupts = <
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0xf 0x4 /* Ethernet */
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0x9 0x4 /* Ethernet Wake Up */>;
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local-mac-address = [000000000000]; /* Filled in by zImage */
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reg = <0xef600800 0x00000070>;
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mal-device = <&MAL>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <1500>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rmii";
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phy-map = <0x00000000>;
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};
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};
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EBC0: ebc {
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compatible = "ibm,ebc-405gp", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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/* The ranges property is supplied by the bootwrapper
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* and is based on the firmware's configuration of the
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* EBC bridge
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*/
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clock-frequency = <0>; /* Filled in by zImage */
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/* NVRAM and RTC */
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nvrtc@4,200000 {
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compatible = "ds1742";
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reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
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};
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/* "BCSR" CPLD contains a PCI irq controller */
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bcsr@4,0 {
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compatible = "ep405-bcsr";
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reg = <0x00000004 0x00000000 0x00000010>;
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interrupt-controller;
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/* Routing table */
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irq-routing = [ 00 /* SYSERR */
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01 /* STTM */
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01 /* RTC */
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01 /* FENET */
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02 /* NB PCIIRQ mux ? */
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03 /* SB Winbond 8259 ? */
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04 /* Serial Ring */
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05 /* USB (ep405pc) */
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06 /* XIRQ 0 */
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06 /* XIRQ 1 */
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06 /* XIRQ 2 */
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06 /* XIRQ 3 */
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06 /* XIRQ 4 */
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06 /* XIRQ 5 */
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06 /* XIRQ 6 */
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07]; /* Reserved */
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};
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};
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PCI0: pci@ec000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
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primary;
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reg = <0xeec00000 0x00000008 /* Config space access */
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0xeed80000 0x00000004 /* IACK */
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0xeed80000 0x00000004 /* Special cycle */
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0xef480000 0x00000040>; /* Internal registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed. Chip supports a second
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* IO range but we don't use it for now
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
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0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
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/* That's all I know about IRQs on that thing ... */
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interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
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interrupt-map = <
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/* USB */
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0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
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>;
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};
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};
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chosen {
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stdout-path = "/plb/opb/serial@ef600300";
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};
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};
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@ -1,71 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Embedded Planet EP405 with PlanetCore firmware
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*
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* (c) Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp,\
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*
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* Based on ep88xc.c by
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*
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* Scott Wood <scottwood@freescale.com>
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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*/
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#include "ops.h"
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#include "stdio.h"
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#include "planetcore.h"
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#include "dcr.h"
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#include "4xx.h"
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#include "io.h"
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static char *table;
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static u64 mem_size;
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static void platform_fixups(void)
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{
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u64 val;
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void *nvrtc;
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dt_fixup_memory(0, mem_size);
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planetcore_set_mac_addrs(table);
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if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) {
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printf("No PlanetCore crystal frequency key.\r\n");
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return;
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}
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ibm405gp_fixup_clocks(val, 0xa8c000);
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ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
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ibm4xx_fixup_ebc_ranges("/plb/ebc");
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if (!planetcore_get_decimal(table, PLANETCORE_KEY_KB_NVRAM, &val)) {
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printf("No PlanetCore NVRAM size key.\r\n");
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return;
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}
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nvrtc = finddevice("/plb/ebc/nvrtc@4,200000");
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if (nvrtc != NULL) {
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u32 reg[3] = { 4, 0x200000, 0};
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getprop(nvrtc, "reg", reg, 3);
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reg[2] = (val << 10) & 0xffffffff;
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setprop(nvrtc, "reg", reg, 3);
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}
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}
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void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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table = (char *)r3;
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planetcore_prepare_table(table);
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if (!planetcore_get_decimal(table, PLANETCORE_KEY_MB_RAM, &mem_size))
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return;
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mem_size *= 1024 * 1024;
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simple_alloc_init(_end, mem_size - (unsigned long)_end, 32, 64);
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fdt_init(_dtb_start);
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planetcore_set_stdout_path(table);
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serial_console_init();
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platform_ops.fixups = platform_fixups;
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}
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@ -1,62 +0,0 @@
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CONFIG_40x=y
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_EXPERT=y
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CONFIG_KALLSYMS_ALL=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_EP405=y
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# CONFIG_WALNUT is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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# CONFIG_IPV6 is not set
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CONFIG_CONNECTOR=y
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CONFIG_MTD=y
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_BLOCK=m
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CONFIG_MTD_CFI=y
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CONFIG_MTD_JEDECPROBE=y
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=35000
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CONFIG_NETDEVICES=y
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CONFIG_IBM_EMAC=y
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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CONFIG_THERMAL=y
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CONFIG_USB=y
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CONFIG_USB_MON=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
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CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
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CONFIG_EXT2_FS=y
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CONFIG_PROC_KCORE=y
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CONFIG_TMPFS=y
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CONFIG_CRAMFS=y
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CONFIG_NFS_FS=y
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CONFIG_ROOT_NFS=y
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CONFIG_DEBUG_FS=y
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CONFIG_MAGIC_SYSRQ=y
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||||
CONFIG_DETECT_HUNG_TASK=y
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||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_PCBC=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
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@ -10,7 +10,6 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PPC4xx_GPIO=y
|
||||
CONFIG_ACADIA=y
|
||||
CONFIG_EP405=y
|
||||
CONFIG_HOTFOOT=y
|
||||
CONFIG_KILAUEA=y
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||||
CONFIG_MAKALU=y
|
||||
|
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|
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|
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@ -7,14 +7,6 @@ config ACADIA
|
|||
help
|
||||
This option enables support for the AMCC 405EZ Acadia evaluation board.
|
||||
|
||||
config EP405
|
||||
bool "EP405/EP405PC"
|
||||
depends on 40x
|
||||
select 405GP
|
||||
select FORCE_PCI
|
||||
help
|
||||
This option enables support for the EP405/EP405PC boards.
|
||||
|
||||
config HOTFOOT
|
||||
bool "Hotfoot"
|
||||
depends on 40x
|
||||
|
|
|
|||
|
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@ -1,3 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_EP405) += ep405.o
|
||||
obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o
|
||||
|
|
|
|||
|
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@ -1,123 +0,0 @@
|
|||
/*
|
||||
* Architecture- / platform-specific boot-time initialization code for
|
||||
* IBM PowerPC 4xx based boards. Adapted from original
|
||||
* code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
|
||||
* <dan@net4x.com>.
|
||||
*
|
||||
* Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
|
||||
*
|
||||
* Rewritten and ported to the merged powerpc tree:
|
||||
* Copyright 2007 IBM Corporation
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Adapted to EP405 by Ben. Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
* TODO: Wire up the PCI IRQ mux and the southbridge interrupts
|
||||
*
|
||||
* 2002 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/uic.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
static struct device_node *bcsr_node;
|
||||
static void __iomem *bcsr_regs;
|
||||
|
||||
/* BCSR registers */
|
||||
#define BCSR_ID 0
|
||||
#define BCSR_PCI_CTRL 1
|
||||
#define BCSR_FLASH_NV_POR_CTRL 2
|
||||
#define BCSR_FENET_UART_CTRL 3
|
||||
#define BCSR_PCI_IRQ 4
|
||||
#define BCSR_XIRQ_SELECT 5
|
||||
#define BCSR_XIRQ_ROUTING 6
|
||||
#define BCSR_XIRQ_STATUS 7
|
||||
#define BCSR_XIRQ_STATUS2 8
|
||||
#define BCSR_SW_STAT_LED_CTRL 9
|
||||
#define BCSR_GPIO_IRQ_PAR_CTRL 10
|
||||
/* there's more, can't be bothered typing them tho */
|
||||
|
||||
|
||||
static const struct of_device_id ep405_of_bus[] __initconst = {
|
||||
{ .compatible = "ibm,plb3", },
|
||||
{ .compatible = "ibm,opb", },
|
||||
{ .compatible = "ibm,ebc", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init ep405_device_probe(void)
|
||||
{
|
||||
of_platform_bus_probe(NULL, ep405_of_bus, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_device_initcall(ep405, ep405_device_probe);
|
||||
|
||||
static void __init ep405_init_bcsr(void)
|
||||
{
|
||||
const u8 *irq_routing;
|
||||
int i;
|
||||
|
||||
/* Find the bloody thing & map it */
|
||||
bcsr_node = of_find_compatible_node(NULL, NULL, "ep405-bcsr");
|
||||
if (bcsr_node == NULL) {
|
||||
printk(KERN_ERR "EP405 BCSR not found !\n");
|
||||
return;
|
||||
}
|
||||
bcsr_regs = of_iomap(bcsr_node, 0);
|
||||
if (bcsr_regs == NULL) {
|
||||
printk(KERN_ERR "EP405 BCSR failed to map !\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get the irq-routing property and apply the routing to the CPLD */
|
||||
irq_routing = of_get_property(bcsr_node, "irq-routing", NULL);
|
||||
if (irq_routing == NULL)
|
||||
return;
|
||||
for (i = 0; i < 16; i++) {
|
||||
u8 irq = irq_routing[i];
|
||||
out_8(bcsr_regs + BCSR_XIRQ_SELECT, i);
|
||||
out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq);
|
||||
}
|
||||
in_8(bcsr_regs + BCSR_XIRQ_SELECT);
|
||||
mb();
|
||||
out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe);
|
||||
}
|
||||
|
||||
static void __init ep405_setup_arch(void)
|
||||
{
|
||||
/* Find & init the BCSR CPLD */
|
||||
ep405_init_bcsr();
|
||||
|
||||
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
|
||||
}
|
||||
|
||||
static int __init ep405_probe(void)
|
||||
{
|
||||
if (!of_machine_is_compatible("ep405"))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
define_machine(ep405) {
|
||||
.name = "EP405",
|
||||
.probe = ep405_probe,
|
||||
.setup_arch = ep405_setup_arch,
|
||||
.progress = udbg_progress,
|
||||
.init_IRQ = uic_init_tree,
|
||||
.get_irq = uic_get_irq,
|
||||
.restart = ppc4xx_reset_system,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
};
|
||||
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