Merge branch 'fixes-dss' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
This commit is contained in:
Arnd Bergmann
Коммит
55135dfbf3
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@ -4,7 +4,7 @@
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# Common support
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obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
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common.o gpio.o dma.o wd_timer.o
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common.o gpio.o dma.o wd_timer.o display.o
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omap-2-3-common = irq.o sdrc.o
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hwmod-common = omap_hwmod.o \
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@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
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obj-y += $(smsc911x-m) $(smsc911x-y)
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obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
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disp-$(CONFIG_OMAP2_DSS) := display.o
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obj-y += $(disp-m) $(disp-y)
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obj-y += common-board-devices.o twl-common.o
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@ -27,8 +27,35 @@
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include <plat/omap-pm.h>
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#include <plat/common.h>
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#include "control.h"
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#include "display.h"
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#define DISPC_CONTROL 0x0040
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#define DISPC_CONTROL2 0x0238
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#define DISPC_IRQSTATUS 0x0018
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#define DSS_SYSCONFIG 0x10
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#define DSS_SYSSTATUS 0x14
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#define DSS_CONTROL 0x40
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#define DSS_SDI_CONTROL 0x44
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#define DSS_PLL_CONTROL 0x48
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#define LCD_EN_MASK (0x1 << 0)
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#define DIGIT_EN_MASK (0x1 << 1)
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#define FRAMEDONE_IRQ_SHIFT 0
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#define EVSYNC_EVEN_IRQ_SHIFT 2
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#define EVSYNC_ODD_IRQ_SHIFT 3
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#define FRAMEDONE2_IRQ_SHIFT 22
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#define FRAMEDONETV_IRQ_SHIFT 24
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/*
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* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
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* reset before deciding that something has gone wrong
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*/
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#define FRAMEDONE_IRQ_TIMEOUT 100
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static struct platform_device omap_display_device = {
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.name = "omapdss",
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@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
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return r;
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}
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static void dispc_disable_outputs(void)
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{
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u32 v, irq_mask = 0;
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bool lcd_en, digit_en, lcd2_en = false;
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int i;
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struct omap_dss_dispc_dev_attr *da;
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struct omap_hwmod *oh;
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oh = omap_hwmod_lookup("dss_dispc");
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if (!oh) {
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WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
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return;
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}
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if (!oh->dev_attr) {
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pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
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return;
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}
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da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
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/* store value of LCDENABLE and DIGITENABLE bits */
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v = omap_hwmod_read(oh, DISPC_CONTROL);
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lcd_en = v & LCD_EN_MASK;
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digit_en = v & DIGIT_EN_MASK;
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/* store value of LCDENABLE for LCD2 */
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if (da->manager_count > 2) {
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v = omap_hwmod_read(oh, DISPC_CONTROL2);
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lcd2_en = v & LCD_EN_MASK;
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}
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if (!(lcd_en | digit_en | lcd2_en))
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return; /* no managers currently enabled */
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/*
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* If any manager was enabled, we need to disable it before
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* DSS clocks are disabled or DISPC module is reset
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*/
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if (lcd_en)
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irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
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if (digit_en) {
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if (da->has_framedonetv_irq) {
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irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
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} else {
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irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
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1 << EVSYNC_ODD_IRQ_SHIFT;
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}
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}
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if (lcd2_en)
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irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
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/*
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* clear any previous FRAMEDONE, FRAMEDONETV,
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* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
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*/
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omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
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/* disable LCD and TV managers */
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v = omap_hwmod_read(oh, DISPC_CONTROL);
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v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
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omap_hwmod_write(v, oh, DISPC_CONTROL);
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/* disable LCD2 manager */
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if (da->manager_count > 2) {
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v = omap_hwmod_read(oh, DISPC_CONTROL2);
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v &= ~LCD_EN_MASK;
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omap_hwmod_write(v, oh, DISPC_CONTROL2);
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}
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i = 0;
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while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
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irq_mask) {
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i++;
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if (i > FRAMEDONE_IRQ_TIMEOUT) {
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pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
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break;
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}
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mdelay(1);
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}
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}
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#define MAX_MODULE_SOFTRESET_WAIT 10000
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int omap_dss_reset(struct omap_hwmod *oh)
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{
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struct omap_hwmod_opt_clk *oc;
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int c = 0;
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int i, r;
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if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
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pr_err("dss_core: hwmod data doesn't contain reset data\n");
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return -EINVAL;
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}
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for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
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if (oc->_clk)
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clk_enable(oc->_clk);
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dispc_disable_outputs();
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/* clear SDI registers */
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if (cpu_is_omap3430()) {
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omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
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omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
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}
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/*
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* clear DSS_CONTROL register to switch DSS clock sources to
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* PRCM clock, if any
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*/
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omap_hwmod_write(0x0, oh, DSS_CONTROL);
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omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("dss_core: waiting for reset to finish failed\n");
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else
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pr_debug("dss_core: softreset done\n");
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for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
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if (oc->_clk)
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clk_disable(oc->_clk);
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r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
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return r;
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}
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@ -0,0 +1,29 @@
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/*
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* display.h - OMAP2+ integration-specific DSS header
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
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#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
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#include <linux/kernel.h>
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struct omap_dss_dispc_dev_attr {
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u8 manager_count;
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bool has_framedonetv_irq;
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};
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#endif
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@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
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};
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static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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/*
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* The DSS HW needs all DSS clocks enabled during reset. The dss_core
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* driver does not use these clocks.
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*/
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{ .role = "tv_clk", .clk = "dss_54m_fck" },
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{ .role = "sys_clk", .clk = "dss2_fck" },
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};
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@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
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.masters = omap2420_dss_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
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.flags = HWMOD_NO_IDLEST,
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.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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};
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/* l4_core -> dss_dispc */
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@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
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.slaves = omap2420_dss_dispc_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
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.flags = HWMOD_NO_IDLEST,
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.dev_attr = &omap2_3_dss_dispc_dev_attr
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};
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/* l4_core -> dss_rfbi */
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@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
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&omap2420_l4_core__dss_rfbi,
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};
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static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
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{ .role = "ick", .clk = "dss_ick" },
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};
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static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
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.name = "dss_rfbi",
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.class = &omap2_rfbi_hwmod_class,
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@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
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.module_offs = CORE_MOD,
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},
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},
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.opt_clks = dss_rfbi_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
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.slaves = omap2420_dss_rfbi_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
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.flags = HWMOD_NO_IDLEST,
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@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
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static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_dss_venc_hwmod,
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.clk = "dss_54m_fck",
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.clk = "dss_ick",
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.addr = omap2_dss_venc_addrs,
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.fw = {
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.omap2 = {
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@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
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static struct omap_hwmod omap2420_dss_venc_hwmod = {
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.name = "dss_venc",
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.class = &omap2_venc_hwmod_class,
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.main_clk = "dss1_fck",
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.main_clk = "dss_54m_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
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};
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static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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/*
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* The DSS HW needs all DSS clocks enabled during reset. The dss_core
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* driver does not use these clocks.
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*/
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{ .role = "tv_clk", .clk = "dss_54m_fck" },
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{ .role = "sys_clk", .clk = "dss2_fck" },
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};
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@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
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.slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
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.masters = omap2430_dss_masters,
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.masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
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.flags = HWMOD_NO_IDLEST,
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.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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};
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/* l4_core -> dss_dispc */
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@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
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.slaves = omap2430_dss_dispc_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
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.flags = HWMOD_NO_IDLEST,
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.dev_attr = &omap2_3_dss_dispc_dev_attr
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};
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/* l4_core -> dss_rfbi */
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@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
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&omap2430_l4_core__dss_rfbi,
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};
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static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
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{ .role = "ick", .clk = "dss_ick" },
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};
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static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
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.name = "dss_rfbi",
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.class = &omap2_rfbi_hwmod_class,
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@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
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.module_offs = CORE_MOD,
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},
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},
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.opt_clks = dss_rfbi_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
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.slaves = omap2430_dss_rfbi_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
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.flags = HWMOD_NO_IDLEST,
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@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
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static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
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.master = &omap2430_l4_core_hwmod,
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.slave = &omap2430_dss_venc_hwmod,
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.clk = "dss_54m_fck",
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.clk = "dss_ick",
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.addr = omap2_dss_venc_addrs,
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.flags = OCPIF_SWSUP_IDLE,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
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static struct omap_hwmod omap2430_dss_venc_hwmod = {
|
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.name = "dss_venc",
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.class = &omap2_venc_hwmod_class,
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.main_clk = "dss1_fck",
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.main_clk = "dss_54m_fck",
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.prcm = {
|
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.omap2 = {
|
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.prcm_reg_id = 1,
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|
|
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@ -11,6 +11,7 @@
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#include <plat/omap_hwmod.h>
|
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#include <plat/serial.h>
|
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#include <plat/dma.h>
|
||||
#include <plat/common.h>
|
||||
|
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#include <mach/irqs.h>
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|
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@ -43,13 +44,15 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
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SYSS_HAS_RESET_STATUS),
|
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.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_dss_hwmod_class = {
|
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.name = "dss",
|
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.sysc = &omap2_dss_sysc,
|
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.reset = omap_dss_reset,
|
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};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
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@ -1369,9 +1369,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
|
|||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
|
||||
{ .role = "tv_clk", .clk = "dss_tv_fck" },
|
||||
{ .role = "video_clk", .clk = "dss_96m_fck" },
|
||||
/*
|
||||
* The DSS HW needs all DSS clocks enabled during reset. The dss_core
|
||||
* driver does not use these clocks.
|
||||
*/
|
||||
{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
|
||||
{ .role = "tv_clk", .clk = "dss_tv_fck" },
|
||||
/* required only on OMAP3430 */
|
||||
{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3430es1_dss_core_hwmod = {
|
||||
|
|
@ -1394,11 +1399,12 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
|
|||
.slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
|
||||
.masters = omap3xxx_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_dss_core_hwmod = {
|
||||
.name = "dss_core",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.class = &omap2_dss_hwmod_class,
|
||||
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
|
||||
.sdma_reqs = omap3xxx_dss_sdma_chs,
|
||||
|
|
@ -1456,6 +1462,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
|
|||
.slaves = omap3xxx_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.dev_attr = &omap2_3_dss_dispc_dev_attr
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1486,6 +1493,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
|
|||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_dsi1_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap3xxx_dss_dsi1_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
|
|
@ -1502,6 +1510,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
|
|||
&omap3xxx_l4_core__dss_dsi1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
|
||||
{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
|
||||
.name = "dss_dsi1",
|
||||
.class = &omap3xxx_dsi_hwmod_class,
|
||||
|
|
@ -1514,6 +1526,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
|
|||
.module_offs = OMAP3430_DSS_MOD,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_dsi1_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
|
||||
.slaves = omap3xxx_dss_dsi1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
|
|
@ -1540,6 +1554,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
|
|||
&omap3xxx_l4_core__dss_rfbi,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
|
||||
{ .role = "ick", .clk = "dss_ick" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
|
||||
.name = "dss_rfbi",
|
||||
.class = &omap2_rfbi_hwmod_class,
|
||||
|
|
@ -1551,6 +1569,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
|
|||
.module_offs = OMAP3430_DSS_MOD,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_rfbi_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
||||
.slaves = omap3xxx_dss_rfbi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
|
|
@ -1560,7 +1580,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
|
|||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_venc_hwmod,
|
||||
.clk = "dss_tv_fck",
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
|
|
@ -1578,10 +1598,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
|
|||
&omap3xxx_l4_core__dss_venc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
|
||||
/* required only on OMAP3430 */
|
||||
{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
|
||||
.name = "dss_venc",
|
||||
.class = &omap2_venc_hwmod_class,
|
||||
.main_clk = "dss1_alwon_fck",
|
||||
.main_clk = "dss_tv_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
|
|
@ -1589,6 +1614,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
|
|||
.module_offs = OMAP3430_DSS_MOD,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_venc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
|
||||
.slaves = omap3xxx_dss_venc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#include <plat/mmc.h>
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/dmtimer.h>
|
||||
#include <plat/common.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
|
|
@ -1187,6 +1188,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
|
|||
static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
|
||||
.name = "dss",
|
||||
.sysc = &omap44xx_dss_sysc,
|
||||
.reset = omap_dss_reset,
|
||||
};
|
||||
|
||||
/* dss */
|
||||
|
|
@ -1240,12 +1242,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
|
|||
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
|
||||
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
||||
{ .role = "tv_clk", .clk = "dss_tv_clk" },
|
||||
{ .role = "dss_clk", .clk = "dss_dss_clk" },
|
||||
{ .role = "video_clk", .clk = "dss_48mhz_clk" },
|
||||
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dss_hwmod = {
|
||||
.name = "dss_core",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.class = &omap44xx_dss_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.main_clk = "dss_dss_clk",
|
||||
|
|
@ -1325,6 +1327,11 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
|
||||
.manager_count = 3,
|
||||
.has_framedonetv_irq = 1
|
||||
};
|
||||
|
||||
/* l4_per -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
|
|
@ -1340,12 +1347,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
|
|||
&omap44xx_l4_per__dss_dispc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
|
||||
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
||||
{ .role = "tv_clk", .clk = "dss_tv_clk" },
|
||||
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap44xx_dispc_hwmod_class,
|
||||
|
|
@ -1359,10 +1360,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
|||
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_dispc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
|
||||
.slaves = omap44xx_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
|
||||
.dev_attr = &omap44xx_dss_dispc_dev_attr
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1624,7 +1624,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
|||
.clkdm_name = "l3_dss_clkdm",
|
||||
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
||||
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
||||
.main_clk = "dss_dss_clk",
|
||||
.main_clk = "dss_48mhz_clk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
||||
|
|
@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
|||
.name = "dss_venc",
|
||||
.class = &omap44xx_venc_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.main_clk = "dss_dss_clk",
|
||||
.main_clk = "dss_tv_clk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
||||
|
|
|
|||
|
|
@ -49,3 +49,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
|
|||
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
|
||||
};
|
||||
|
||||
struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
|
||||
.manager_count = 2,
|
||||
.has_framedonetv_irq = 0
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
#include "display.h"
|
||||
|
||||
/* Common address space across OMAP2xxx */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
|
||||
|
|
@ -111,4 +113,6 @@ extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
|
|||
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_mcspi_class;
|
||||
|
||||
extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/delay.h>
|
||||
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
struct sys_timer;
|
||||
|
||||
|
|
@ -55,6 +56,8 @@ void am35xx_init_early(void);
|
|||
void ti816x_init_early(void);
|
||||
void omap4430_init_early(void);
|
||||
|
||||
extern int omap_dss_reset(struct omap_hwmod *);
|
||||
|
||||
void omap_sram_init(void);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -307,15 +307,8 @@ struct omap_dss_board_info {
|
|||
void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
|
||||
};
|
||||
|
||||
#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
|
||||
/* Init with the board info */
|
||||
extern int omap_display_init(struct omap_dss_board_info *board_data);
|
||||
#else
|
||||
static inline int omap_display_init(struct omap_dss_board_info *board_data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct omap_display_platform_data {
|
||||
struct omap_dss_board_info *board_data;
|
||||
|
|
|
|||
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