A boring time, timekeeping, timers update:
- No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmM9dgsTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoeg4D/9rJefRINQRwSQuoLfky42SLy5OZXlA OwAZn0waUNwAXyp8pJd+WO5ZD4lcOmBlgPWNDKW3cLo8+uGzZpHTuTQMBnnHzyek ny4y4haRySPR8KQF9Jr+JLmMZtQhUESVTUDZYSwtbka1zM3ys6rJOGBDV/fwCCK+ gSdvRjNCN3TtIkNtxWWsAF/Sk8ucK22shztsIRiqL2eCPuKmJ0gZUChnCs69ue+D K98B7qH/IPMMtVtgX/yTEpSZxyjGVXakW1IvL3Y4Zxwc7G6OGEiDLSmIEj0pGtYr Vt4yTvauIY7PL212J7agL1EcG7wwFy1pANaeZAIHgpewjc959b0q41Ht2bAMYH1Q hgNgRCn47v7Iz5Ko/QycTK4NoEqqEZtfwvLMEo55bi0RxcOGDpexQOtaLM1BCtJy EFOsdQr2NMQguKcn5qvOVW3+HJuLnYsvbHSGCIAoXHB93UtDM/edg8BCNJHGyTtH 9u/iv2hiKPYBjUG95NPo+mictuL5CmSaYNMlSdzDR5L/Eeke3Qp1zMPAxFK6FjTU eVi6C472n83C/EpGMpfi+ms2UK3E3Dy8QgwNEJN0mTzEHXPUCjdXFWEI72jeYyHy dV8rSzDg6B82iaZ17eVqCTL4GGyo+kT2a3j3qaUC/rp0MDys7yYkBI6csRTvETdQ ARwPYYQYkuEEeQ== =n458 -----END PGP SIGNATURE----- Merge tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "A boring time, timekeeping, timers update: - No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place" * tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value clocksource/drivers/imx-sysctr: handle nxp,no-divider property dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() clocksource/drivers/timer-ti-dm: Add flag to detect omap1 clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors clocksource/drivers/timer-ti-dm: Move private defines to the driver clocksource/drivers/timer-ti-dm: Simplify register access further clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write() clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read() clocksource/drivers/timer-ti-dm: Drop unused functions clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921 clocksource/drivers/exynos_mct: Enable building on ARTPEC clocksource/drivers/exynos_mct: Support local-timers property clocksource/drivers/exynos_mct: Support frc-shared property dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support clocksource/drivers/sun4i: Add definition of clear interrupt clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC ...
This commit is contained in:
Linus Torvalds
Коммит
55be6084c8
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@ -25,6 +25,7 @@ Required properties:
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For those SoCs that use SYST
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* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
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* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
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* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
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* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
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* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
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* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
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@ -32,6 +32,10 @@ properties:
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clock-names:
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const: per
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nxp,no-divider:
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description: if present, means there is no internal base clk divider.
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type: boolean
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required:
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- compatible
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- reg
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@ -37,6 +37,7 @@ properties:
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- renesas,tmu-r8a77990 # R-Car E3
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- renesas,tmu-r8a77995 # R-Car D3
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- renesas,tmu-r8a779a0 # R-Car V3U
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- renesas,tmu-r8a779f0 # R-Car S4-8
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- const: renesas,tmu
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reg:
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@ -25,6 +25,7 @@ properties:
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- samsung,exynos4412-mct
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- items:
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- enum:
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- axis,artpec8-mct
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- samsung,exynos3250-mct
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- samsung,exynos5250-mct
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- samsung,exynos5260-mct
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@ -45,6 +46,19 @@ properties:
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reg:
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maxItems: 1
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samsung,frc-shared:
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type: boolean
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description: |
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Indicates that the hardware requires that this processor share the
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free-running counter with a different (main) processor.
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samsung,local-timers:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 16
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description: |
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List of indices of local timers usable from this processor.
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interrupts:
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description: |
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Interrupts should be put in specific order. This is, the local timer
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@ -74,6 +88,17 @@ required:
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- reg
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allOf:
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- axis,artpec8-mct
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then:
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properties:
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samsung,local-timers: false
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samsung,frc-shared: false
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- if:
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properties:
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compatible:
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@ -101,6 +126,7 @@ allOf:
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compatible:
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contains:
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enum:
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- axis,artpec8-mct
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- samsung,exynos5260-mct
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- samsung,exynos5420-mct
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- samsung,exynos5433-mct
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@ -434,7 +434,7 @@ config ATMEL_TCB_CLKSRC
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config CLKSRC_EXYNOS_MCT
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bool "Exynos multi core timer driver" if COMPILE_TEST
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depends on ARM || ARM64
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depends on ARCH_EXYNOS || COMPILE_TEST
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depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST
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help
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Support for Multi Core Timer controller on Exynos SoCs.
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@ -44,8 +44,8 @@
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#define CNTACR_RWVT BIT(4)
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#define CNTACR_RWPT BIT(5)
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#define CNTVCT_LO 0x00
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#define CNTPCT_LO 0x08
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#define CNTPCT_LO 0x00
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#define CNTVCT_LO 0x08
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#define CNTFRQ 0x10
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#define CNTP_CVAL_LO 0x20
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#define CNTP_CTL 0x2c
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@ -473,6 +473,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.desc = "ARM erratum 858921",
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.read_cntpct_el0 = arm64_858921_read_cntpct_el0,
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.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
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.set_next_event_phys = erratum_set_next_event_phys,
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.set_next_event_virt = erratum_set_next_event_virt,
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},
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#endif
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#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
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@ -33,7 +33,7 @@
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#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
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#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
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#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
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#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
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#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x)))
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#define EXYNOS4_MCT_L_MASK (0xffffff00)
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#define MCT_L_TCNTB_OFFSET (0x00)
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@ -66,6 +66,8 @@
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#define MCT_L0_IRQ 4
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/* Max number of IRQ as per DT binding document */
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#define MCT_NR_IRQS 20
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/* Max number of local timers */
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#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ)
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enum {
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MCT_INT_SPI,
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@ -233,9 +235,16 @@ static cycles_t exynos4_read_current_timer(void)
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}
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#endif
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static int __init exynos4_clocksource_init(void)
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static int __init exynos4_clocksource_init(bool frc_shared)
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{
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exynos4_mct_frc_start();
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/*
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* When the frc is shared, the main processer should have already
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* turned it on and we shouldn't be writing to TCON.
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*/
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if (frc_shared)
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mct_frc.resume = NULL;
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else
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exynos4_mct_frc_start();
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#if defined(CONFIG_ARM)
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exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
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@ -449,7 +458,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu)
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per_cpu_ptr(&percpu_mct_tick, cpu);
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struct clock_event_device *evt = &mevt->evt;
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mevt->base = EXYNOS4_MCT_L_BASE(cpu);
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snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
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evt->name = mevt->name;
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@ -520,8 +528,17 @@ static int __init exynos4_timer_resources(struct device_node *np)
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return 0;
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}
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/**
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* exynos4_timer_interrupts - initialize MCT interrupts
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* @np: device node for MCT
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* @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI
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* @local_idx: array mapping CPU numbers to local timer indices
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* @nr_local: size of @local_idx array
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*/
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static int __init exynos4_timer_interrupts(struct device_node *np,
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unsigned int int_type)
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unsigned int int_type,
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const u32 *local_idx,
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size_t nr_local)
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{
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int nr_irqs, i, err, cpu;
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@ -554,13 +571,21 @@ static int __init exynos4_timer_interrupts(struct device_node *np,
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} else {
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for_each_possible_cpu(cpu) {
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int mct_irq;
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unsigned int irq_idx;
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struct mct_clock_event_device *pcpu_mevt =
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per_cpu_ptr(&percpu_mct_tick, cpu);
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if (cpu >= nr_local) {
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err = -EINVAL;
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goto out_irq;
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}
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irq_idx = MCT_L0_IRQ + local_idx[cpu];
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pcpu_mevt->evt.irq = -1;
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if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs))
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if (irq_idx >= ARRAY_SIZE(mct_irqs))
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break;
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mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
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mct_irq = mct_irqs[irq_idx];
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irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
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if (request_irq(mct_irq,
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@ -576,6 +601,17 @@ static int __init exynos4_timer_interrupts(struct device_node *np,
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}
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}
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for_each_possible_cpu(cpu) {
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struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu);
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if (cpu >= nr_local) {
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err = -EINVAL;
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goto out_irq;
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}
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mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]);
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}
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/* Install hotplug callbacks which configure the timer on this CPU */
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err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
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"clockevents/exynos4/mct_timer:starting",
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@ -605,20 +641,49 @@ out_irq:
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static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
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{
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bool frc_shared = of_property_read_bool(np, "samsung,frc-shared");
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u32 local_idx[MCT_NR_LOCAL] = {0};
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int nr_local;
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int ret;
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nr_local = of_property_count_u32_elems(np, "samsung,local-timers");
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if (nr_local == 0)
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return -EINVAL;
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if (nr_local > 0) {
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if (nr_local > ARRAY_SIZE(local_idx))
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return -EINVAL;
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ret = of_property_read_u32_array(np, "samsung,local-timers",
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local_idx, nr_local);
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if (ret)
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return ret;
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} else {
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int i;
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nr_local = ARRAY_SIZE(local_idx);
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for (i = 0; i < nr_local; i++)
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local_idx[i] = i;
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}
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ret = exynos4_timer_resources(np);
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if (ret)
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return ret;
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ret = exynos4_timer_interrupts(np, int_type);
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ret = exynos4_timer_interrupts(np, int_type, local_idx, nr_local);
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if (ret)
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return ret;
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ret = exynos4_clocksource_init();
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ret = exynos4_clocksource_init(frc_shared);
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if (ret)
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return ret;
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/*
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* When the FRC is shared with a main processor, this secondary
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* processor cannot use the global comparator.
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*/
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if (frc_shared)
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return ret;
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return exynos4_clockevent_init();
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}
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|
|
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@ -224,7 +224,7 @@ err_free:
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TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
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#ifdef CONFIG_ARCH_R9A07G044
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#ifdef CONFIG_ARCH_RZG2L
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static int __init ostm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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|
|
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@ -171,6 +171,7 @@ static int gxp_timer_probe(struct platform_device *pdev)
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{
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struct platform_device *gxp_watchdog_device;
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struct device *dev = &pdev->dev;
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int ret;
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if (!gxp_timer) {
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pr_err("Gxp Timer not initialized, cannot create watchdog");
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@ -187,7 +188,11 @@ static int gxp_timer_probe(struct platform_device *pdev)
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gxp_watchdog_device->dev.platform_data = gxp_timer->counter;
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gxp_watchdog_device->dev.parent = dev;
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return platform_device_add(gxp_watchdog_device);
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ret = platform_device_add(gxp_watchdog_device);
|
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if (ret)
|
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platform_device_put(gxp_watchdog_device);
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return ret;
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}
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static const struct of_device_id gxp_timer_of_match[] = {
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|
|
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@ -134,8 +134,10 @@ static int __init sysctr_timer_init(struct device_node *np)
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if (ret)
|
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return ret;
|
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|
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/* system counter clock is divided by 3 internally */
|
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to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
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if (!of_property_read_bool(np, "nxp,no-divider")) {
|
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/* system counter clock is divided by 3 internally */
|
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to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
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}
|
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|
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sys_ctr_base = timer_of_base(&to_sysctr);
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cmpcr = readl(sys_ctr_base + CMPCR);
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|
|
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@ -26,6 +26,7 @@
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) BIT(val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_IRQ_CLEAR(val) BIT(val)
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#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE BIT(0)
|
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#define TIMER_CTL_RELOAD BIT(1)
|
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|
|
@ -123,7 +124,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
|
|||
|
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static void sun4i_timer_clear_interrupt(void __iomem *base)
|
||||
{
|
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writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
|
||||
writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
|
||||
}
|
||||
|
||||
static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -52,10 +52,6 @@
|
|||
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
|
||||
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
|
||||
|
||||
/* posted mode types */
|
||||
#define OMAP_TIMER_NONPOSTED 0x00
|
||||
#define OMAP_TIMER_POSTED 0x01
|
||||
|
||||
/* timer capabilities used in hwmod database */
|
||||
#define OMAP_TIMER_SECURE 0x80000000
|
||||
#define OMAP_TIMER_ALWON 0x40000000
|
||||
|
|
@ -63,73 +59,13 @@
|
|||
#define OMAP_TIMER_NEEDS_RESET 0x10000000
|
||||
#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
|
||||
|
||||
/*
|
||||
* timer errata flags
|
||||
*
|
||||
* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
|
||||
* errata prevents us from using posted mode on these devices, unless the
|
||||
* timer counter register is never read. For more details please refer to
|
||||
* the OMAP3/4/5 errata documents.
|
||||
*/
|
||||
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
|
||||
|
||||
struct timer_regs {
|
||||
u32 ocp_cfg;
|
||||
u32 tidr;
|
||||
u32 tier;
|
||||
u32 twer;
|
||||
u32 tclr;
|
||||
u32 tcrr;
|
||||
u32 tldr;
|
||||
u32 ttrg;
|
||||
u32 twps;
|
||||
u32 tmar;
|
||||
u32 tcar1;
|
||||
u32 tsicr;
|
||||
u32 tcar2;
|
||||
u32 tpir;
|
||||
u32 tnir;
|
||||
u32 tcvr;
|
||||
u32 tocr;
|
||||
u32 towr;
|
||||
};
|
||||
|
||||
struct omap_dm_timer {
|
||||
int id;
|
||||
int irq;
|
||||
struct clk *fclk;
|
||||
|
||||
void __iomem *io_base;
|
||||
void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
|
||||
void __iomem *irq_ena; /* irq enable */
|
||||
void __iomem *irq_dis; /* irq disable, only on v2 ip */
|
||||
void __iomem *pend; /* write pending */
|
||||
void __iomem *func_base; /* function register base */
|
||||
|
||||
atomic_t enabled;
|
||||
unsigned long rate;
|
||||
unsigned reserved:1;
|
||||
unsigned posted:1;
|
||||
struct timer_regs context;
|
||||
int revision;
|
||||
u32 capability;
|
||||
u32 errata;
|
||||
struct platform_device *pdev;
|
||||
struct list_head node;
|
||||
struct notifier_block nb;
|
||||
};
|
||||
|
||||
int omap_dm_timer_reserve_systimer(int id);
|
||||
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
|
||||
|
||||
int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
|
||||
|
||||
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
|
||||
|
||||
int omap_dm_timer_trigger(struct omap_dm_timer *timer);
|
||||
|
||||
int omap_dm_timers_active(void);
|
||||
|
||||
/*
|
||||
* Do not use the defines below, they are not needed. They should be only
|
||||
* used by dmtimer.c and sys_timer related code.
|
||||
|
|
@ -199,52 +135,4 @@ int omap_dm_timers_active(void);
|
|||
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
|
||||
|
||||
/* register offsets with the write pending bit encoded */
|
||||
#define WPSHIFT 16
|
||||
|
||||
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
|
||||
| (WP_TCLR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
|
||||
| (WP_TCRR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
|
||||
| (WP_TLDR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
|
||||
| (WP_TTGR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
|
||||
| (WP_TMAR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
|
||||
| (WP_TPIR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
|
||||
| (WP_TNIR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
|
||||
| (WP_TCVR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
|
||||
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
|
||||
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
|
||||
|
||||
#endif /* __CLOCKSOURCE_DMTIMER_H */
|
||||
|
|
|
|||
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