clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible PHY clock parent. Export it so it can be used later in DT. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Родитель
b1a1ad4b75
Коммит
55de0f31df
|
@ -26,7 +26,9 @@
|
|||
#define CLK_PLL_AUDIO_2X 3
|
||||
#define CLK_PLL_AUDIO_4X 4
|
||||
#define CLK_PLL_AUDIO_8X 5
|
||||
#define CLK_PLL_VIDEO 6
|
||||
|
||||
/* PLL_VIDEO is exported */
|
||||
|
||||
#define CLK_PLL_VE 7
|
||||
#define CLK_PLL_DDR 8
|
||||
|
||||
|
|
|
@ -43,6 +43,8 @@
|
|||
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
|
||||
#define CLK_PLL_VIDEO 6
|
||||
|
||||
#define CLK_PLL_PERIPH0 9
|
||||
|
||||
#define CLK_CPUX 14
|
||||
|
|
Загрузка…
Ссылка в новой задаче