V4L/DVB: tvp7002: fix write to H-PLL Feedback Divider LSB register
H-PLL Feedback Divider LSB register is an 8 bit register out of which the first 4 bits are reserved. Current code is writing to these reserved location. This patch corrects this issue by left shifting the values being written to the register by 4. This patch has been tested on DM6467 EVM with 720P-60 and 1080I-60 inputs. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Родитель
d0a38ce27e
Коммит
560afa7d85
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@ -179,7 +179,7 @@ static const struct i2c_reg_value tvp7002_init_default[] = {
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/* Register parameters for 480P */
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/* Register parameters for 480P */
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static const struct i2c_reg_value tvp7002_parms_480P[] = {
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static const struct i2c_reg_value tvp7002_parms_480P[] = {
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x0a, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
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@ -223,7 +223,7 @@ static const struct i2c_reg_value tvp7002_parms_576P[] = {
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/* Register parameters for 1080I60 */
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/* Register parameters for 1080I60 */
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static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
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static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x08, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
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@ -245,7 +245,7 @@ static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
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/* Register parameters for 1080P60 */
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/* Register parameters for 1080P60 */
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static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
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static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x08, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
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@ -289,7 +289,7 @@ static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
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/* Register parameters for 720P60 */
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/* Register parameters for 720P60 */
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static const struct i2c_reg_value tvp7002_parms_720P60[] = {
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static const struct i2c_reg_value tvp7002_parms_720P60[] = {
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x02, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
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@ -311,7 +311,7 @@ static const struct i2c_reg_value tvp7002_parms_720P60[] = {
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/* Register parameters for 720P50 */
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/* Register parameters for 720P50 */
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static const struct i2c_reg_value tvp7002_parms_720P50[] = {
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static const struct i2c_reg_value tvp7002_parms_720P50[] = {
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x0c, TVP7002_WRITE },
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{ TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
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{ TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
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{ TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
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{ TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
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